This introduces support for the following devices:
- Lenovo Thinkpad T14s Gen 6
- Microsoft Surface Laptop 7 laptop
- Lenovo A6000
- Lenovo A6010
- Samsung Galaxy J3,
- Lenovo Vibe K5 (multiple variants)
- LG G4
IPQ5332 global clock controller is marked as an interconnect-provider,
and the USB interrupt triggers are corrected.
Touchscreen description is added to the Samsung Galaxy Core Prime and
Max, and touch keys are added to the Samsung Galaxy Grand Prime and
Galaxy Tab A.
Camera flash is added to BQ Aquaris M5 and X5.
The SD-card slot is described for the QCM6490 IDP.
For SA8775P CPU and LLCC bwmon is added, audio, compute and general
purpose DSP remoteprocs are added, with FastRPC on audio and compute
DSP. CPUidle states, capacity and DPC properties are added.
On SC8180X definitions for the multiport USB controller is introduced,
and enabled on the Lenovo Flex 5G to bring the camera to life. Power key
definitions are added as well.
The RGB camera sensor on the Lenovo ThinkPad X13s is described. PCIe
pinconf properties are cleaned up on this and the CRD. The four USB
Type-A ports found on the SA8295P ADP are enabled.
The modem subsystem remoteproc is introduced on the SDX75 and enabled on
the IDP device.
Camera, display and GPU clock controllers are added for the SM4450
platform.
On the F(x)tec Pro1X device, display, GPU, WiFi, RGB LED, SD-card,
remoteprocs, USB3 SuperSpeed, touchscreen, IO-expander, hall switch,
caps lock LED and camera button are introduced.
The camera clock controller is added to SM8150, and the GPU-only
"amd,imageon" compatible is dropped from the MTP device.
Refgen regulator for the DSI nodes of SM8350 is described, and the
display subsystem interconnect paths are corrected.
The camera control interface controllers are described on both SM8550
and SM8650. The bluetooth node on on SM8550 QRD, SM8650 QRD and SM8650
HDK are transitioned to the power sequence description. WiFi is added to
the SM8550 hardware development kit (HDK).
On the X1 Elite platform, one more UART, a DisplayPort PHY, the USB
multiport controller, a PCIe controller and PHY are added. Orientation
switching is wired up for the USB+DP PHYs. RPMh statistics node is
added. For the X1 Elite CRD the LID switch and the SDX65 modems are
introduced.
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Merge tag 'qcom-arm64-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm64 DeviceTree updates for v6.12
This introduces support for the following devices:
- Lenovo Thinkpad T14s Gen 6
- Microsoft Surface Laptop 7 laptop
- Lenovo A6000
- Lenovo A6010
- Samsung Galaxy J3,
- Lenovo Vibe K5 (multiple variants)
- LG G4
IPQ5332 global clock controller is marked as an interconnect-provider,
and the USB interrupt triggers are corrected.
Touchscreen description is added to the Samsung Galaxy Core Prime and
Max, and touch keys are added to the Samsung Galaxy Grand Prime and
Galaxy Tab A.
Camera flash is added to BQ Aquaris M5 and X5.
The SD-card slot is described for the QCM6490 IDP.
For SA8775P CPU and LLCC bwmon is added, audio, compute and general
purpose DSP remoteprocs are added, with FastRPC on audio and compute
DSP. CPUidle states, capacity and DPC properties are added.
On SC8180X definitions for the multiport USB controller is introduced,
and enabled on the Lenovo Flex 5G to bring the camera to life. Power key
definitions are added as well.
The RGB camera sensor on the Lenovo ThinkPad X13s is described. PCIe
pinconf properties are cleaned up on this and the CRD. The four USB
Type-A ports found on the SA8295P ADP are enabled.
The modem subsystem remoteproc is introduced on the SDX75 and enabled on
the IDP device.
Camera, display and GPU clock controllers are added for the SM4450
platform.
On the F(x)tec Pro1X device, display, GPU, WiFi, RGB LED, SD-card,
remoteprocs, USB3 SuperSpeed, touchscreen, IO-expander, hall switch,
caps lock LED and camera button are introduced.
The camera clock controller is added to SM8150, and the GPU-only
"amd,imageon" compatible is dropped from the MTP device.
Refgen regulator for the DSI nodes of SM8350 is described, and the
display subsystem interconnect paths are corrected.
The camera control interface controllers are described on both SM8550
and SM8650. The bluetooth node on on SM8550 QRD, SM8650 QRD and SM8650
HDK are transitioned to the power sequence description. WiFi is added to
the SM8550 hardware development kit (HDK).
On the X1 Elite platform, one more UART, a DisplayPort PHY, the USB
multiport controller, a PCIe controller and PHY are added. Orientation
switching is wired up for the USB+DP PHYs. RPMh statistics node is
added. For the X1 Elite CRD the LID switch and the SDX65 modems are
introduced.
* tag 'qcom-arm64-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (120 commits)
arm64: dts: qcom: x1e80100: Fix PHY for DP2
arm64: dts: qcom: qcm6490-idp: Add SD Card node
arm64: dts: qcom: x1e80100: Add orientation-switch to all USB+DP QMP PHYs
arm64: dts: qcom: Add X1E78100 ThinkPad T14s Gen 6
dt-bindings: arm: qcom: Add Lenovo ThinkPad T14s Gen 6
Revert "arm64: dts: qcom: msm8939-longcheer-l9100: Add rear flash"
arm64: dts: qcom: Add support for X1-based Surface Laptop 7 devices
arm64: dts: qcom: x1e80100: Add UART2
arm64: dts: qcom: x1e80100-pmics: Add PMC8380C PWM
dt-bindings: arm: qcom: Add Surface Laptop 7 devices
arm64: dts: qcom: sm8150-mtp: drop incorrect amd,imageon
arm64: qcom: sa8775p: Add ADSP and CDSP0 fastrpc nodes
arm64: dts: qcom: x1e80100: Add USB Multiport controller
arm64: dts: qcom: sa8775p: fix the fastrpc label
arm64: dts: qcom: ipq5332: Add icc provider ability to gcc
dt-bindings: interconnect: Add Qualcomm IPQ5332 support
arm64: dts: qcom: sm8250: move lpass codec macros to use clks directly
arm64: dts: qcom: msm8998: Add disabled support for LPASS iommu for Q6
dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions
arm64: dts: qcom: msm8976: Add restart node
...
Link: https://lore.kernel.org/r/20240904215752.24465-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add support for Ethernet TSN and PCIe on the R-Car V4H SoC and the
White-Hawk (Single) development board,
- Add display support for the RZ/G2UL SoC and the RZ/G2UL SMARC EVk
board,
- Add I2C support for the RZ/G3S SoC and the RZ/G3S SMARC EVK board,
- Add support for HDMI audio on the RZ/G2L and RZ/G2LC SMARC EVK
boards,
- Add initial support for the RZ/V2H(P) (R9A09G057) SoC and the RZ/V2H
EVK board,
- Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v6.12-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.12 (take two)
- Add support for Ethernet TSN and PCIe on the R-Car V4H SoC and the
White-Hawk (Single) development board,
- Add display support for the RZ/G2UL SoC and the RZ/G2UL SMARC EVk
board,
- Add I2C support for the RZ/G3S SoC and the RZ/G3S SMARC EVK board,
- Add support for HDMI audio on the RZ/G2L and RZ/G2LC SMARC EVK
boards,
- Add initial support for the RZ/V2H(P) (R9A09G057) SoC and the RZ/V2H
EVK board,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.12-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (34 commits)
arm64: dts: renesas: r8a779h0: Add family fallback for CSISP IP
arm64: dts: renesas: r8a779a0: Add family fallback for CSISP IP
arm64: dts: renesas: r8a779g0: Add family fallback for CSISP IP
arm64: dts: renesas: r8a779h0: Add family fallback for VIN IP
arm64: dts: renesas: r8a779a0: Add family fallback for VIN IP
arm64: dts: renesas: r8a779g0: Add family fallback for VIN IP
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable watchdog
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable OSTM, I2C, and SDHI
arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
arm64: dts: renesas: r9a09g057: Add SDHI0-SDHI2 nodes
arm64: dts: renesas: r9a09g057: Add RIIC0-RIIC8 nodes
arm64: dts: renesas: r9a09g057: Add OSTM0-OSTM7 nodes
arm64: dts: renesas: Add initial DTS for RZ/V2H EVK board
arm64: dts: renesas: Add initial SoC DTSI for RZ/V2H(P) SoC
dt-bindings: soc: renesas: Document RZ/V2H EVK board
dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG
arm64: dts: renesas: r9a07g043u11-smarc: Enable DU
arm64: dts: renesas: rzg2lc-smarc: Enable HDMI audio
arm64: dts: renesas: rzg2l-smarc: Enable HDMI audio
arm64: dts: renesas: r9a07g043u: Add DU node
...
Link: https://lore.kernel.org/r/cover.1725374275.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Document the device tree bindings for the Renesas RZ/V2H(P) SoC
Clock Pulse Generator (CPG).
CPG block handles the below operations:
- Generation and control of clock signals for the IP modules
- Generation and control of resets
- Control over booting
- Low power consumption and power supply domains
Also define constants for the core clocks of the RZ/V2H(P) SoC. Note the
core clocks are a subset of the ones which are listed as part of section
4.4.2 of HW manual Rev.1.01 which cannot be controlled by CLKON register.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240729202645.263525-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add definitions for the Q6 BIMC, LPASS core and adsp smmu clocks,
required to enable audio functionality on MSM8998.
Add the GDSC definitions for the LPASS_ADSP_GDSC and LPASS_CORE_GDSC
as a final step to enable the required clock tree for the lpass iommu
and for the audio dsp itself.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240814-lpass-v1-1-a5bb8f9dfa8b@freebox.fr
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add device tree bindings for the camera clock controller on
Qualcomm SM4450 platform.
Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240611133752.2192401-5-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add dpum clock definitions and compatibles.
Also used clock name 'bus' instead of full clock name
dout_clkcmu_dpum_bus like other board cmu schema (GS101).
Signed-off-by: Kwanghoon Son <k.son@samsung.com>
Link: https://lore.kernel.org/r/20240809-clk_dpum-v3-1-359decc30fe2@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Exynos7885 SoC has a DWC3 USB Controller with Exynos USB PHY which in
theory supports USB3 SuperSpeed, but is only used as USB2 in all known
devices.
These, of course, need some clocks.
Add indices for these clocks.
Signed-off-by: David Virag <virag.david003@gmail.com>
Link: https://lore.kernel.org/r/20240806121157.479212-4-virag.david003@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The numbering in Exynos7885's FSYS CMU bindings has 4 duplicated by
accident, with the rest of the bindings continuing with 5.
Fix this by moving CLK_MOUT_FSYS_USB30DRD_USER to the end as 11.
Since CLK_MOUT_FSYS_USB30DRD_USER is not used in any device tree as of
now, and there are no other clocks affected (maybe apart from
CLK_MOUT_FSYS_MMC_SDIO_USER which the number was shared with, also not
used in a device tree), this is the least impactful way to solve this
problem.
Fixes: cd268e309c ("dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS")
Cc: stable@vger.kernel.org
Signed-off-by: David Virag <virag.david003@gmail.com>
Link: https://lore.kernel.org/r/20240806121157.479212-2-virag.david003@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Merge the SM8550/SM8650 display clock controller binding header file
merge through a topic branch, to ensure the bindings are kept in sync
between clock and DeviceTree source branches.
The display clock controller indices for SM8650 and SM8550 are
completely equal. Replace the header file for qcom,sm8650-dispcc with
the symlink to the qcom,sm8550-dispcc header file.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-7-5c4a3128c40b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add device tree bindings for the camera clock controller on
Qualcomm SM8150 platform.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240731062916.2680823-7-quic_skakitap@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The USB multiport controller needs a few missing resets, describe them
in the binding.
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20240730-sc8180x-usb-mp-v2-1-a7dc4265b553@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add a constant for TMU PCLK clock. It acts simultaneously as an
interface clock (to access TMU registers) and an operating clock which
makes TMU IP-core functional.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240723163311.28654-1-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
CLK_NR_CLKS should not be part of the binding.
Remove since the kernel code no longer uses it.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/6f21c09b-e8d2-4749-aca6-572c79df775d@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Merge SM8650 video and camera clock drivers through topic branch, to
make available the DeviceTree binding includes to the DeviceTree source
branches as well.
Add device tree bindings for the camera clock controller on
Qualcomm SM8650 platform.
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20240602114439.1611-7-quic_jkona@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
SM8650 video clock controller has most clocks same as SM8450,
but it also has few additional clocks and resets. Add device tree
bindings for the video clock controller on Qualcomm SM8650 platform
by defining these additional clocks and resets on top of SM8450.
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20240602114439.1611-3-quic_jkona@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The clock definitions in <dt-bindings/clock/r8a779?-clock.h> were
superseded by those in <dt-bindings/clock/r8a779?-cpg-mssr.h> a long
time ago.
The last DTS user of these files was removed in commit 362b334b17
("ARM: dts: r8a7791: Convert to new CPG/MSSR bindings") in v4.15.
Driver support for the old bindings was removed in commit
58256143cf ("clk: renesas: Remove R-Car Gen2 legacy DT clock
support") in v5.5, so there is no point to keep on carrying these.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/d4abb688d666be35e99577a25b16958cbb4c3c98.1718796005.git.geert+renesas@glider.be
CLK_NR_CLKS should not be part of the binding. Let's drop it, since
the kernel code no longer uses it either.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240606143401.32454-4-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the required clock bindings for the GPADC.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240605172049.231108-2-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Add bindings for the clock generator of divider/mux and gates working
for other subsystem than RP subsystem for Sophgo SG2042.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Add bindings for the gate clocks of RP subsystem for Sophgo SG2042.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Add bindings for the pll clocks for Sophgo SG2042.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
QCA8386/QCA8084 includes the clock & reset controller that is
accessed by MDIO bus. Two work modes are supported, qca8386 works
as switch mode, qca8084 works as PHY mode.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20240605124541.2711467-3-quic_luoj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The 'sys_pll' input is an optional clock that can be used to generate
'sys_pll_div16', which serves as one of the sources for the GEN clock.
Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240515185103.20256-5-ddrokosov@salutedevices.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
The 'syspll' PLL is a general-purpose PLL designed specifically for the
CPU clock. It is capable of producing output frequencies within the
range of 768MHz to 1536MHz.
The 'syspll_in' source clock is an optional parent connection from the
peripherals clock controller.
Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240515185103.20256-3-ddrokosov@salutedevices.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
The DPHY's APB clock is required to be exposed in order to be able to
enable it and access the phy's registers.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240509140653.168591-3-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add device tree bindings for the video clock controller on Qualcomm
SM7150 platform.
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240505201038.276047-8-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add device tree bindings for the camera clock controller on Qualcomm
SM7150 platform.
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240505201038.276047-6-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add device tree bindings for the display clock controller on Qualcomm
SM7150 platform.
Co-developed-by: David Wronek <david@mainlining.org>
Signed-off-by: David Wronek <david@mainlining.org>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240505201038.276047-4-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
drivers. And there's zero diff in the core clk framework. Instead we have new
clk drivers for STM and Sophgo, with Samsung^WGoogle in third for the diffstat
because they introduced HSI0 and HSI2 clk drivers for Google's GS101 SoC (high
speed interface things like PCIe, UFS, and MMC). Beyond those big diffs there's
the usual updates to various clk drivers for incorrect parent descriptions or
mising MODULE_DEVICE_TABLE()s, etc. Nothing in particular stands out as super
interesting here.
New Drivers:
- STM32MP257 SoC clk driver
- Airoha EN7581 SoC clk driver
- Sophgo CV1800B, CV1812H and SG2000 SoC clk driver
- Loongson-2k0500 and Loongson-2k2000 SoC clk driver
- Add HSI0 and HSI2 clock controllers for Google GS101
- Add i.MX95 BLK CTL clock driver
Updates:
- Allocate clk_ops dynamically for SCMI clk driver
- Add support in qcom RCG and RCG2 for multiple configurations for the same frequency
- Use above support for IPQ8074 NSS port 5 and 6 clocks to resolve issues
- Fix the Qualcomm APSS IPQ5018 PLL to fix boot failures of some boards
- Cleanups and fixes for Qualcomm Stromer PLLs
- Reduce max CPU frequency on Qualcomm APSS IPQ5018
- Fix Kconfig dependencies of Qualcomm SM8650 GPU and SC8280XP camera
clk drivers
- Make Qualcomm MSM8998 Venus clocks functional
- Cleanup downstream remnants related to DisplayPort across Qualcomm
SM8450, SM6350, SM8550, and SM8650
- Reuse the Huayra APSS register map on Qualcomm MSM8996 CBF PLL
- Use a specific Qualcomm QCS404 compatible for the otherwise generic
HFPLL
- Remove Qualcomm SM8150 CPUSS AHB clk as it is unused
- Remove an unused field in the Qualcomm RPM clk driver
- Add missing MODULE_DEVICE_TABLE to Qualcomm MSM8917 and MSM8953
global clock controller drivers
- Allow choice of manual or firmware-driven control over PLLs, needed
to fully implement CPU clock controllers on Exynos850
- Correct PLL clock IDs on ExynosAutov9
- Propagate certain clock rates to allow setting proper SPI clock
rates on Google GS101
- Mark certain Google GS101 clocks critical
- Convert old S3C64xx clock controller bindings to DT schema
- Add new PLL rate and missing mux on Rockchip rk3568
- Add missing reset line on Rockchip rk3588
- Removal of an unused field in struct rockchip_mmc_clock
- Amlogic s4/a1: add regmap maximum register for proper debugfs dump
- Amlogic s4: add MODULE_DEVICE_TABLE() on pll and periph controllers
- Amlogic pll driver: print clock name on lock error to help debug
- Amlogic vclk: finish dsi clock path support
- Amlogic license: fix occurence "GPL v2" as reported by checkpatch
- Add PM runtime support to i.MX8MP Audiomix
- Add DT schema for i.MX95 Display Master Block Control
- Convert to platform remove callback returning void for i.MX8MP
Audiomix
- Add SPI (MSIOF) and external interrupt (INTC-EX) clocks on Renesas R-Car V4M
- Add interrupt controller (PLIC) clock and reset on Renesas RZ/Five
- Prepare power domain support for Renesas RZ/G2L family members, and add
actual support on Renesas RZ/G3S SoC
- Add thermal, serial (SCIF), and timer (CMT/TMU) clocks on Renesas R-Car V4M
- Add additional constraints to Allwinner A64 PLL MIPI clock
- Fix autoloading sunxi-ng clocks when build as a module
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"I'm actually surprised this time. There aren't any new Qualcomm SoC
clk drivers. And there's zero diff in the core clk framework.
Instead we have new clk drivers for STM and Sophgo, with
Samsung^WGoogle in third for the diffstat because they introduced HSI0
and HSI2 clk drivers for Google's GS101 SoC (high speed interface
things like PCIe, UFS, and MMC).
Beyond those big diffs there's the usual updates to various clk
drivers for incorrect parent descriptions or mising
MODULE_DEVICE_TABLE()s, etc. Nothing in particular stands out as super
interesting here.
New Drivers:
- STM32MP257 SoC clk driver
- Airoha EN7581 SoC clk driver
- Sophgo CV1800B, CV1812H and SG2000 SoC clk driver
- Loongson-2k0500 and Loongson-2k2000 SoC clk driver
- Add HSI0 and HSI2 clock controllers for Google GS101
- Add i.MX95 BLK CTL clock driver
Updates:
- Allocate clk_ops dynamically for SCMI clk driver
- Add support in qcom RCG and RCG2 for multiple configurations for
the same frequency
- Use above support for IPQ8074 NSS port 5 and 6 clocks to resolve
issues
- Fix the Qualcomm APSS IPQ5018 PLL to fix boot failures of some
boards
- Cleanups and fixes for Qualcomm Stromer PLLs
- Reduce max CPU frequency on Qualcomm APSS IPQ5018
- Fix Kconfig dependencies of Qualcomm SM8650 GPU and SC8280XP camera
clk drivers
- Make Qualcomm MSM8998 Venus clocks functional
- Cleanup downstream remnants related to DisplayPort across Qualcomm
SM8450, SM6350, SM8550, and SM8650
- Reuse the Huayra APSS register map on Qualcomm MSM8996 CBF PLL
- Use a specific Qualcomm QCS404 compatible for the otherwise generic
HFPLL
- Remove Qualcomm SM8150 CPUSS AHB clk as it is unused
- Remove an unused field in the Qualcomm RPM clk driver
- Add missing MODULE_DEVICE_TABLE to Qualcomm MSM8917 and MSM8953
global clock controller drivers
- Allow choice of manual or firmware-driven control over PLLs, needed
to fully implement CPU clock controllers on Exynos850
- Correct PLL clock IDs on ExynosAutov9
- Propagate certain clock rates to allow setting proper SPI clock
rates on Google GS101
- Mark certain Google GS101 clocks critical
- Convert old S3C64xx clock controller bindings to DT schema
- Add new PLL rate and missing mux on Rockchip rk3568
- Add missing reset line on Rockchip rk3588
- Removal of an unused field in struct rockchip_mmc_clock
- Amlogic s4/a1: add regmap maximum register for proper debugfs dump
- Amlogic s4: add MODULE_DEVICE_TABLE() on pll and periph controllers
- Amlogic pll driver: print clock name on lock error to help debug
- Amlogic vclk: finish dsi clock path support
- Amlogic license: fix occurence "GPL v2" as reported by checkpatch
- Add PM runtime support to i.MX8MP Audiomix
- Add DT schema for i.MX95 Display Master Block Control
- Convert to platform remove callback returning void for i.MX8MP
Audiomix
- Add SPI (MSIOF) and external interrupt (INTC-EX) clocks on Renesas
R-Car V4M
- Add interrupt controller (PLIC) clock and reset on Renesas RZ/Five
- Prepare power domain support for Renesas RZ/G2L family members, and
add actual support on Renesas RZ/G3S SoC
- Add thermal, serial (SCIF), and timer (CMT/TMU) clocks on Renesas
R-Car V4M
- Add additional constraints to Allwinner A64 PLL MIPI clock
- Fix autoloading sunxi-ng clocks when build as a module"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (118 commits)
clk: samsung: Don't register clkdev lookup for the fixed rate clocks
clk, reset: microchip: mpfs: fix incorrect preprocessor conditions
clk: qcom: clk-alpha-pll: fix rate setting for Stromer PLLs
clk: qcom: apss-ipq-pll: fix PLL rate for IPQ5018
clk: qcom: Fix SM_GPUCC_8650 dependencies
clk: qcom: Fix SC_CAMCC_8280XP dependencies
dt-bindings: clocks: stm32mp25: add access-controllers description
clock, reset: microchip: move all mpfs reset code to the reset subsystem
clk: samsung: gs101: drop unused HSI2 clock parent data
clk: rockchip: rk3568: Add PLL rate for 724 MHz
clk: rockchip: Remove an unused field in struct rockchip_mmc_clock
dt-bindings: clock: fixed: Define a preferred node name
clk: meson: s4: fix module autoloading
clk: samsung: gs101: mark some apm UASC and XIU clocks critical
clk: imx: imx8mp: Convert to platform remove callback returning void
clk: imx: imx8mp: Switch to RUNTIME_PM_OPS()
clk: bcm: rpi: Assign ->num before accessing ->hws
clk: bcm: dvp: Assign ->num before accessing ->hws
clk: samsung: gs101: add support for cmu_hsi2
clk: samsung: gs101: add support for cmu_hsi0
...
Arnd Bergmann