647 lines
15 KiB
ArmAsm
647 lines
15 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#include <asm/asm.h>
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#include <asm/loongarch.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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#define INVTLB_ADDR_GFALSE_AND_ASID 5
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#define PTRS_PER_PGD_BITS (PAGE_SHIFT - PTRLOG)
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#define PTRS_PER_PUD_BITS (PAGE_SHIFT - PTRLOG)
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#define PTRS_PER_PMD_BITS (PAGE_SHIFT - PTRLOG)
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#define PTRS_PER_PTE_BITS (PAGE_SHIFT - PTRLOG)
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#ifdef CONFIG_32BIT
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#define PTE_LL ll.w
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#define PTE_SC sc.w
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#else
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#define PTE_LL ll.d
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#define PTE_SC sc.d
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#endif
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.macro tlb_do_page_fault, write
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SYM_CODE_START(tlb_do_page_fault_\write)
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UNWIND_HINT_UNDEFINED
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SAVE_ALL
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csrrd a2, LOONGARCH_CSR_BADV
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move a0, sp
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REG_S a2, sp, PT_BVADDR
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li.w a1, \write
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bl do_page_fault
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RESTORE_ALL_AND_RET
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SYM_CODE_END(tlb_do_page_fault_\write)
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.endm
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tlb_do_page_fault 0
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tlb_do_page_fault 1
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SYM_CODE_START(handle_tlb_protect)
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UNWIND_HINT_UNDEFINED
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BACKUP_T0T1
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SAVE_ALL
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move a0, sp
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move a1, zero
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csrrd a2, LOONGARCH_CSR_BADV
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REG_S a2, sp, PT_BVADDR
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la_abs t0, do_page_fault
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jirl ra, t0, 0
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RESTORE_ALL_AND_RET
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SYM_CODE_END(handle_tlb_protect)
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SYM_CODE_START(handle_tlb_load)
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UNWIND_HINT_UNDEFINED
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csrwr t0, EXCEPTION_KS0
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csrwr t1, EXCEPTION_KS1
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csrwr ra, EXCEPTION_KS2
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/*
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* The vmalloc handling is not in the hotpath.
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*/
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csrrd t0, LOONGARCH_CSR_BADV
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bltz t0, vmalloc_load
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csrrd t1, LOONGARCH_CSR_PGDL
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vmalloc_done_load:
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/* Get PGD offset in bytes */
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#ifdef CONFIG_32BIT
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PTR_BSTRPICK ra, t0, 31, PGDIR_SHIFT
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#else
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PTR_BSTRPICK ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT
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#endif
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PTR_ALSL t1, ra, t1, _PGD_T_LOG2
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#if CONFIG_PGTABLE_LEVELS > 3
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PTR_L t1, t1, 0
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PTR_BSTRPICK ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT
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PTR_ALSL t1, ra, t1, _PMD_T_LOG2
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#endif
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#if CONFIG_PGTABLE_LEVELS > 2
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PTR_L t1, t1, 0
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PTR_BSTRPICK ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT
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PTR_ALSL t1, ra, t1, _PMD_T_LOG2
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#endif
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PTR_L ra, t1, 0
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/*
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* For huge tlb entries, pmde doesn't contain an address but
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* instead contains the tlb pte. Check the PAGE_HUGE bit and
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* see if we need to jump to huge tlb processing.
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*/
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PTR_ROTRI ra, ra, _PAGE_HUGE_SHIFT + 1
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bltz ra, tlb_huge_update_load
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PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1)
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PTR_BSTRPICK t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT
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PTR_ALSL t1, t0, ra, _PTE_T_LOG2
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#ifdef CONFIG_SMP
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smp_pgtable_change_load:
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PTE_LL t0, t1, 0
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#else
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PTR_L t0, t1, 0
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#endif
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andi ra, t0, _PAGE_PRESENT
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beqz ra, nopage_tlb_load
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ori t0, t0, _PAGE_VALID
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#ifdef CONFIG_SMP
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PTE_SC t0, t1, 0
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beqz t0, smp_pgtable_change_load
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#else
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PTR_S t0, t1, 0
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#endif
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tlbsrch
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PTR_BSTRINS t1, zero, _PTE_T_LOG2, _PTE_T_LOG2
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PTR_L t0, t1, 0
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PTR_L t1, t1, _PTE_T_SIZE
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csrwr t0, LOONGARCH_CSR_TLBELO0
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csrwr t1, LOONGARCH_CSR_TLBELO1
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tlbwr
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csrrd t0, EXCEPTION_KS0
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csrrd t1, EXCEPTION_KS1
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csrrd ra, EXCEPTION_KS2
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ertn
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vmalloc_load:
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la_abs t1, swapper_pg_dir
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b vmalloc_done_load
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/* This is the entry point of a huge page. */
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tlb_huge_update_load:
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#ifdef CONFIG_SMP
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PTE_LL ra, t1, 0
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#else
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PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1)
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#endif
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andi t0, ra, _PAGE_PRESENT
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beqz t0, nopage_tlb_load
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#ifdef CONFIG_SMP
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ori t0, ra, _PAGE_VALID
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PTE_SC t0, t1, 0
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beqz t0, tlb_huge_update_load
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ori t0, ra, _PAGE_VALID
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#else
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ori t0, ra, _PAGE_VALID
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PTR_S t0, t1, 0
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#endif
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csrrd ra, LOONGARCH_CSR_ASID
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csrrd t1, LOONGARCH_CSR_BADV
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andi ra, ra, CSR_ASID_ASID
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invtlb INVTLB_ADDR_GFALSE_AND_ASID, ra, t1
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/*
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* A huge PTE describes an area the size of the
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* configured huge page size. This is twice the
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* of the large TLB entry size we intend to use.
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* A TLB entry half the size of the configured
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* huge page size is configured into entrylo0
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* and entrylo1 to cover the contiguous huge PTE
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* address space.
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*/
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/* Huge page: Move Global bit */
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xori t0, t0, _PAGE_HUGE
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lu12i.w t1, _PAGE_HGLOBAL >> 12
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and t1, t0, t1
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PTR_SRLI t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT)
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or t0, t0, t1
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move ra, t0
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csrwr ra, LOONGARCH_CSR_TLBELO0
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/* Convert to entrylo1 */
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PTR_ADDI t1, zero, 1
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PTR_SLLI t1, t1, (HPAGE_SHIFT - 1)
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PTR_ADD t0, t0, t1
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csrwr t0, LOONGARCH_CSR_TLBELO1
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/* Set huge page tlb entry size */
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PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16
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PTR_LI t1, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT))
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csrxchg t1, t0, LOONGARCH_CSR_TLBIDX
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tlbfill
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PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16
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PTR_LI t1, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT))
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csrxchg t1, t0, LOONGARCH_CSR_TLBIDX
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csrrd t0, EXCEPTION_KS0
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csrrd t1, EXCEPTION_KS1
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csrrd ra, EXCEPTION_KS2
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ertn
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nopage_tlb_load:
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dbar 0x700
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csrrd ra, EXCEPTION_KS2
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la_abs t0, tlb_do_page_fault_0
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jr t0
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SYM_CODE_END(handle_tlb_load)
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SYM_CODE_START(handle_tlb_load_ptw)
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UNWIND_HINT_UNDEFINED
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csrwr t0, LOONGARCH_CSR_KS0
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csrwr t1, LOONGARCH_CSR_KS1
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la_abs t0, tlb_do_page_fault_0
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jr t0
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SYM_CODE_END(handle_tlb_load_ptw)
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SYM_CODE_START(handle_tlb_store)
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UNWIND_HINT_UNDEFINED
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csrwr t0, EXCEPTION_KS0
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csrwr t1, EXCEPTION_KS1
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csrwr ra, EXCEPTION_KS2
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/*
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* The vmalloc handling is not in the hotpath.
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*/
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csrrd t0, LOONGARCH_CSR_BADV
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bltz t0, vmalloc_store
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csrrd t1, LOONGARCH_CSR_PGDL
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vmalloc_done_store:
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/* Get PGD offset in bytes */
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#ifdef CONFIG_32BIT
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PTR_BSTRPICK ra, t0, 31, PGDIR_SHIFT
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#else
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PTR_BSTRPICK ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT
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#endif
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PTR_ALSL t1, ra, t1, _PGD_T_LOG2
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#if CONFIG_PGTABLE_LEVELS > 3
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PTR_L t1, t1, 0
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PTR_BSTRPICK ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT
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PTR_ALSL t1, ra, t1, _PMD_T_LOG2
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#endif
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#if CONFIG_PGTABLE_LEVELS > 2
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PTR_L t1, t1, 0
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PTR_BSTRPICK ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT
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PTR_ALSL t1, ra, t1, _PMD_T_LOG2
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#endif
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PTR_L ra, t1, 0
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/*
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* For huge tlb entries, pmde doesn't contain an address but
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* instead contains the tlb pte. Check the PAGE_HUGE bit and
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* see if we need to jump to huge tlb processing.
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*/
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PTR_ROTRI ra, ra, _PAGE_HUGE_SHIFT + 1
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bltz ra, tlb_huge_update_store
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PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1)
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PTR_BSTRPICK t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT
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PTR_ALSL t1, t0, ra, _PTE_T_LOG2
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#ifdef CONFIG_SMP
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smp_pgtable_change_store:
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PTE_LL t0, t1, 0
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#else
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PTR_L t0, t1, 0
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#endif
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#ifdef CONFIG_64BIT
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andi ra, t0, _PAGE_PRESENT | _PAGE_WRITE
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xori ra, ra, _PAGE_PRESENT | _PAGE_WRITE
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#else
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PTR_LI ra, _PAGE_PRESENT | _PAGE_WRITE
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and ra, ra, t0
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nor ra, ra, zero
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#endif
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bnez ra, nopage_tlb_store
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#ifdef CONFIG_64BIT
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ori t0, t0, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
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#else
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PTR_LI ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
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or t0, ra, t0
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#endif
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#ifdef CONFIG_SMP
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PTE_SC t0, t1, 0
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beqz t0, smp_pgtable_change_store
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#else
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PTR_S t0, t1, 0
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#endif
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tlbsrch
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PTR_BSTRINS t1, zero, _PTE_T_LOG2, _PTE_T_LOG2
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PTR_L t0, t1, 0
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PTR_L t1, t1, _PTE_T_SIZE
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csrwr t0, LOONGARCH_CSR_TLBELO0
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csrwr t1, LOONGARCH_CSR_TLBELO1
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tlbwr
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csrrd t0, EXCEPTION_KS0
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csrrd t1, EXCEPTION_KS1
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csrrd ra, EXCEPTION_KS2
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ertn
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vmalloc_store:
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la_abs t1, swapper_pg_dir
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b vmalloc_done_store
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/* This is the entry point of a huge page. */
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tlb_huge_update_store:
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#ifdef CONFIG_SMP
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PTE_LL ra, t1, 0
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#else
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PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1)
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#endif
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#ifdef CONFIG_64BIT
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andi t0, ra, _PAGE_PRESENT | _PAGE_WRITE
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xori t0, t0, _PAGE_PRESENT | _PAGE_WRITE
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#else
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PTR_LI t0, _PAGE_PRESENT | _PAGE_WRITE
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and t0, t0, ra
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nor t0, t0, zero
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#endif
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bnez t0, nopage_tlb_store
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#ifdef CONFIG_SMP
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ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
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PTE_SC t0, t1, 0
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beqz t0, tlb_huge_update_store
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ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
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#else
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#ifdef CONFIG_64BIT
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ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
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#else
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PTR_LI t0, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
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or t0, ra, t0
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#endif
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PTR_S t0, t1, 0
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#endif
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csrrd ra, LOONGARCH_CSR_ASID
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csrrd t1, LOONGARCH_CSR_BADV
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andi ra, ra, CSR_ASID_ASID
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invtlb INVTLB_ADDR_GFALSE_AND_ASID, ra, t1
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/*
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* A huge PTE describes an area the size of the
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* configured huge page size. This is twice the
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* of the large TLB entry size we intend to use.
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* A TLB entry half the size of the configured
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* huge page size is configured into entrylo0
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* and entrylo1 to cover the contiguous huge PTE
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* address space.
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*/
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/* Huge page: Move Global bit */
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xori t0, t0, _PAGE_HUGE
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lu12i.w t1, _PAGE_HGLOBAL >> 12
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and t1, t0, t1
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PTR_SRLI t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT)
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or t0, t0, t1
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move ra, t0
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csrwr ra, LOONGARCH_CSR_TLBELO0
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/* Convert to entrylo1 */
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PTR_ADDI t1, zero, 1
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PTR_SLLI t1, t1, (HPAGE_SHIFT - 1)
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PTR_ADD t0, t0, t1
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csrwr t0, LOONGARCH_CSR_TLBELO1
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/* Set huge page tlb entry size */
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PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16
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PTR_LI t1, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT))
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csrxchg t1, t0, LOONGARCH_CSR_TLBIDX
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tlbfill
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/* Reset default page size */
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PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16
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PTR_LI t1, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT))
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csrxchg t1, t0, LOONGARCH_CSR_TLBIDX
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csrrd t0, EXCEPTION_KS0
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csrrd t1, EXCEPTION_KS1
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csrrd ra, EXCEPTION_KS2
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ertn
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nopage_tlb_store:
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dbar 0x700
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csrrd ra, EXCEPTION_KS2
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la_abs t0, tlb_do_page_fault_1
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jr t0
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SYM_CODE_END(handle_tlb_store)
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SYM_CODE_START(handle_tlb_store_ptw)
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UNWIND_HINT_UNDEFINED
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csrwr t0, LOONGARCH_CSR_KS0
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csrwr t1, LOONGARCH_CSR_KS1
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la_abs t0, tlb_do_page_fault_1
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jr t0
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SYM_CODE_END(handle_tlb_store_ptw)
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SYM_CODE_START(handle_tlb_modify)
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UNWIND_HINT_UNDEFINED
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csrwr t0, EXCEPTION_KS0
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csrwr t1, EXCEPTION_KS1
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csrwr ra, EXCEPTION_KS2
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/*
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* The vmalloc handling is not in the hotpath.
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*/
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csrrd t0, LOONGARCH_CSR_BADV
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bltz t0, vmalloc_modify
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csrrd t1, LOONGARCH_CSR_PGDL
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vmalloc_done_modify:
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/* Get PGD offset in bytes */
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#ifdef CONFIG_32BIT
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PTR_BSTRPICK ra, t0, 31, PGDIR_SHIFT
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#else
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PTR_BSTRPICK ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT
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#endif
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PTR_ALSL t1, ra, t1, _PGD_T_LOG2
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#if CONFIG_PGTABLE_LEVELS > 3
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PTR_L t1, t1, 0
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PTR_BSTRPICK ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT
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PTR_ALSL t1, ra, t1, _PMD_T_LOG2
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#endif
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#if CONFIG_PGTABLE_LEVELS > 2
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PTR_L t1, t1, 0
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PTR_BSTRPICK ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT
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PTR_ALSL t1, ra, t1, _PMD_T_LOG2
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#endif
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PTR_L ra, t1, 0
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/*
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* For huge tlb entries, pmde doesn't contain an address but
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* instead contains the tlb pte. Check the PAGE_HUGE bit and
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* see if we need to jump to huge tlb processing.
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*/
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PTR_ROTRI ra, ra, _PAGE_HUGE_SHIFT + 1
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bltz ra, tlb_huge_update_modify
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PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1)
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PTR_BSTRPICK t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT
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PTR_ALSL t1, t0, ra, _PTE_T_LOG2
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#ifdef CONFIG_SMP
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smp_pgtable_change_modify:
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PTE_LL t0, t1, 0
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#else
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PTR_L t0, t1, 0
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#endif
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#ifdef CONFIG_64BIT
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andi ra, t0, _PAGE_WRITE
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#else
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PTR_LI ra, _PAGE_WRITE
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and ra, t0, ra
|
|
#endif
|
|
|
|
beqz ra, nopage_tlb_modify
|
|
|
|
#ifdef CONFIG_64BIT
|
|
ori t0, t0, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
|
#else
|
|
PTR_LI ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
|
or t0, ra, t0
|
|
#endif
|
|
|
|
#ifdef CONFIG_SMP
|
|
PTE_SC t0, t1, 0
|
|
beqz t0, smp_pgtable_change_modify
|
|
#else
|
|
PTR_S t0, t1, 0
|
|
#endif
|
|
tlbsrch
|
|
PTR_BSTRINS t1, zero, _PTE_T_LOG2, _PTE_T_LOG2
|
|
PTR_L t0, t1, 0
|
|
PTR_L t1, t1, _PTE_T_SIZE
|
|
csrwr t0, LOONGARCH_CSR_TLBELO0
|
|
csrwr t1, LOONGARCH_CSR_TLBELO1
|
|
tlbwr
|
|
|
|
csrrd t0, EXCEPTION_KS0
|
|
csrrd t1, EXCEPTION_KS1
|
|
csrrd ra, EXCEPTION_KS2
|
|
ertn
|
|
|
|
vmalloc_modify:
|
|
la_abs t1, swapper_pg_dir
|
|
b vmalloc_done_modify
|
|
|
|
/* This is the entry point of a huge page. */
|
|
tlb_huge_update_modify:
|
|
#ifdef CONFIG_SMP
|
|
PTE_LL ra, t1, 0
|
|
#else
|
|
PTR_ROTRI ra, ra, BITS_PER_LONG - (_PAGE_HUGE_SHIFT + 1)
|
|
#endif
|
|
|
|
#ifdef CONFIG_64BIT
|
|
andi t0, ra, _PAGE_WRITE
|
|
#else
|
|
PTR_LI t0, _PAGE_WRITE
|
|
and t0, ra, t0
|
|
#endif
|
|
|
|
beqz t0, nopage_tlb_modify
|
|
|
|
#ifdef CONFIG_SMP
|
|
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
|
PTE_SC t0, t1, 0
|
|
beqz t0, tlb_huge_update_modify
|
|
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
|
#else
|
|
#ifdef CONFIG_64BIT
|
|
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
|
#else
|
|
PTR_LI t0, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
|
|
or t0, ra, t0
|
|
#endif
|
|
PTR_S t0, t1, 0
|
|
#endif
|
|
csrrd ra, LOONGARCH_CSR_ASID
|
|
csrrd t1, LOONGARCH_CSR_BADV
|
|
andi ra, ra, CSR_ASID_ASID
|
|
invtlb INVTLB_ADDR_GFALSE_AND_ASID, ra, t1
|
|
|
|
/*
|
|
* A huge PTE describes an area the size of the
|
|
* configured huge page size. This is twice the
|
|
* of the large TLB entry size we intend to use.
|
|
* A TLB entry half the size of the configured
|
|
* huge page size is configured into entrylo0
|
|
* and entrylo1 to cover the contiguous huge PTE
|
|
* address space.
|
|
*/
|
|
/* Huge page: Move Global bit */
|
|
xori t0, t0, _PAGE_HUGE
|
|
lu12i.w t1, _PAGE_HGLOBAL >> 12
|
|
and t1, t0, t1
|
|
PTR_SRLI t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT)
|
|
or t0, t0, t1
|
|
|
|
move ra, t0
|
|
csrwr ra, LOONGARCH_CSR_TLBELO0
|
|
|
|
/* Convert to entrylo1 */
|
|
PTR_ADDI t1, zero, 1
|
|
PTR_SLLI t1, t1, (HPAGE_SHIFT - 1)
|
|
PTR_ADD t0, t0, t1
|
|
csrwr t0, LOONGARCH_CSR_TLBELO1
|
|
|
|
/* Set huge page tlb entry size */
|
|
PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16
|
|
PTR_LI t1, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT))
|
|
csrxchg t1, t0, LOONGARCH_CSR_TLBIDX
|
|
|
|
tlbfill
|
|
|
|
/* Reset default page size */
|
|
PTR_LI t0, (CSR_TLBIDX_PS >> 16) << 16
|
|
PTR_LI t1, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT))
|
|
csrxchg t1, t0, LOONGARCH_CSR_TLBIDX
|
|
|
|
csrrd t0, EXCEPTION_KS0
|
|
csrrd t1, EXCEPTION_KS1
|
|
csrrd ra, EXCEPTION_KS2
|
|
ertn
|
|
|
|
nopage_tlb_modify:
|
|
dbar 0x700
|
|
csrrd ra, EXCEPTION_KS2
|
|
la_abs t0, tlb_do_page_fault_1
|
|
jr t0
|
|
SYM_CODE_END(handle_tlb_modify)
|
|
|
|
SYM_CODE_START(handle_tlb_modify_ptw)
|
|
UNWIND_HINT_UNDEFINED
|
|
csrwr t0, LOONGARCH_CSR_KS0
|
|
csrwr t1, LOONGARCH_CSR_KS1
|
|
la_abs t0, tlb_do_page_fault_1
|
|
jr t0
|
|
SYM_CODE_END(handle_tlb_modify_ptw)
|
|
|
|
#ifdef CONFIG_32BIT
|
|
SYM_CODE_START(handle_tlb_refill)
|
|
UNWIND_HINT_UNDEFINED
|
|
csrwr t0, EXCEPTION_KS0
|
|
csrwr t1, EXCEPTION_KS1
|
|
csrwr ra, EXCEPTION_KS2
|
|
li.w ra, 0x1fffffff
|
|
|
|
csrrd t0, LOONGARCH_CSR_PGD
|
|
csrrd t1, LOONGARCH_CSR_TLBRBADV
|
|
srli.w t1, t1, PGDIR_SHIFT
|
|
slli.w t1, t1, 0x2
|
|
add.w t0, t0, t1
|
|
and t0, t0, ra
|
|
|
|
ld.w t0, t0, 0
|
|
csrrd t1, LOONGARCH_CSR_TLBRBADV
|
|
slli.w t1, t1, (32 - PGDIR_SHIFT)
|
|
srli.w t1, t1, (32 - PGDIR_SHIFT + PAGE_SHIFT + 1)
|
|
slli.w t1, t1, (0x2 + 1)
|
|
add.w t0, t0, t1
|
|
and t0, t0, ra
|
|
|
|
ld.w t1, t0, 0x0
|
|
csrwr t1, LOONGARCH_CSR_TLBRELO0
|
|
|
|
ld.w t1, t0, 0x4
|
|
csrwr t1, LOONGARCH_CSR_TLBRELO1
|
|
|
|
tlbfill
|
|
csrrd t0, EXCEPTION_KS0
|
|
csrrd t1, EXCEPTION_KS1
|
|
csrrd ra, EXCEPTION_KS2
|
|
ertn
|
|
SYM_CODE_END(handle_tlb_refill)
|
|
#endif
|
|
|
|
#ifdef CONFIG_64BIT
|
|
SYM_CODE_START(handle_tlb_refill)
|
|
UNWIND_HINT_UNDEFINED
|
|
csrwr t0, LOONGARCH_CSR_TLBRSAVE
|
|
csrrd t0, LOONGARCH_CSR_PGD
|
|
lddir t0, t0, 3
|
|
#if CONFIG_PGTABLE_LEVELS > 3
|
|
lddir t0, t0, 2
|
|
#endif
|
|
#if CONFIG_PGTABLE_LEVELS > 2
|
|
lddir t0, t0, 1
|
|
#endif
|
|
ldpte t0, 0
|
|
ldpte t0, 1
|
|
tlbfill
|
|
csrrd t0, LOONGARCH_CSR_TLBRSAVE
|
|
ertn
|
|
SYM_CODE_END(handle_tlb_refill)
|
|
#endif
|