196 lines
5.5 KiB
C
196 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Maxim MAX77705 definitions.
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*
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* Copyright (C) 2015 Samsung Electronics, Inc.
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* Copyright (C) 2025 Dzmitry Sankouski <dsankouski@gmail.com>
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*/
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#ifndef __LINUX_MFD_MAX77705_PRIV_H
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#define __LINUX_MFD_MAX77705_PRIV_H
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#define MAX77705_SRC_IRQ_CHG BIT(0)
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#define MAX77705_SRC_IRQ_TOP BIT(1)
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#define MAX77705_SRC_IRQ_FG BIT(2)
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#define MAX77705_SRC_IRQ_USBC BIT(3)
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#define MAX77705_SRC_IRQ_ALL (MAX77705_SRC_IRQ_CHG | MAX77705_SRC_IRQ_TOP | \
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MAX77705_SRC_IRQ_FG | MAX77705_SRC_IRQ_USBC)
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/* MAX77705_PMIC_REG_PMICREV register */
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#define MAX77705_VERSION_SHIFT 3
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#define MAX77705_REVISION_MASK GENMASK(2, 0)
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#define MAX77705_VERSION_MASK GENMASK(7, MAX77705_VERSION_SHIFT)
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/* MAX77705_PMIC_REG_MAINCTRL1 register */
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#define MAX77705_MAINCTRL1_BIASEN_SHIFT 7
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#define MAX77705_MAINCTRL1_BIASEN_MASK BIT(MAX77705_MAINCTRL1_BIASEN_SHIFT)
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/* MAX77705_PMIC_REG_MCONFIG2 (haptics) register */
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#define MAX77705_CONFIG2_MEN_SHIFT 6
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#define MAX77705_CONFIG2_MODE_SHIFT 7
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#define MAX77705_CONFIG2_HTYP_SHIFT 5
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/* MAX77705_PMIC_REG_SYSTEM_INT_MASK register */
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#define MAX77705_SYSTEM_IRQ_BSTEN_INT BIT(3)
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#define MAX77705_SYSTEM_IRQ_SYSUVLO_INT BIT(4)
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#define MAX77705_SYSTEM_IRQ_SYSOVLO_INT BIT(5)
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#define MAX77705_SYSTEM_IRQ_TSHDN_INT BIT(6)
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#define MAX77705_SYSTEM_IRQ_TM_INT BIT(7)
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/* MAX77705_RGBLED_REG_LEDEN register */
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#define MAX77705_RGBLED_EN_WIDTH 2
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/* MAX77705_RGBLED_REG_LEDBLNK register */
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#define MAX77705_RGB_DELAY_100_STEP_LIM 500
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#define MAX77705_RGB_DELAY_100_STEP_COUNT 4
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#define MAX77705_RGB_DELAY_100_STEP 100
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#define MAX77705_RGB_DELAY_250_STEP_LIM 3250
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#define MAX77705_RGB_DELAY_250_STEP 250
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#define MAX77705_RGB_DELAY_500_STEP 500
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#define MAX77705_RGB_DELAY_500_STEP_COUNT 10
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#define MAX77705_RGB_DELAY_500_STEP_LIM 5000
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#define MAX77705_RGB_DELAY_1000_STEP_LIM 8000
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#define MAX77705_RGB_DELAY_1000_STEP_COUNT 13
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#define MAX77705_RGB_DELAY_1000_STEP 1000
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#define MAX77705_RGB_DELAY_2000_STEP 2000
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#define MAX77705_RGB_DELAY_2000_STEP_COUNT 13
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#define MAX77705_RGB_DELAY_2000_STEP_LIM 12000
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enum max77705_hw_rev {
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MAX77705_PASS1 = 1,
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MAX77705_PASS2,
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MAX77705_PASS3
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};
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enum max77705_reg {
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MAX77705_PMIC_REG_PMICID1 = 0x00,
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MAX77705_PMIC_REG_PMICREV = 0x01,
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MAX77705_PMIC_REG_MAINCTRL1 = 0x02,
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MAX77705_PMIC_REG_BSTOUT_MASK = 0x03,
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MAX77705_PMIC_REG_FORCE_EN_MASK = 0x08,
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MAX77705_PMIC_REG_MCONFIG = 0x10,
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MAX77705_PMIC_REG_MCONFIG2 = 0x11,
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MAX77705_PMIC_REG_INTSRC = 0x22,
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MAX77705_PMIC_REG_INTSRC_MASK = 0x23,
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MAX77705_PMIC_REG_SYSTEM_INT = 0x24,
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MAX77705_PMIC_REG_RESERVED_25 = 0x25,
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MAX77705_PMIC_REG_SYSTEM_INT_MASK = 0x26,
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MAX77705_PMIC_REG_RESERVED_27 = 0x27,
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MAX77705_PMIC_REG_RESERVED_28 = 0x28,
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MAX77705_PMIC_REG_RESERVED_29 = 0x29,
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MAX77705_PMIC_REG_BOOSTCONTROL1 = 0x4C,
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MAX77705_PMIC_REG_BOOSTCONTROL2 = 0x4F,
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MAX77705_PMIC_REG_SW_RESET = 0x50,
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MAX77705_PMIC_REG_USBC_RESET = 0x51,
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MAX77705_PMIC_REG_END
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};
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enum max77705_chg_reg {
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MAX77705_CHG_REG_BASE = 0xB0,
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MAX77705_CHG_REG_INT = 0,
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MAX77705_CHG_REG_INT_MASK,
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MAX77705_CHG_REG_INT_OK,
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MAX77705_CHG_REG_DETAILS_00,
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MAX77705_CHG_REG_DETAILS_01,
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MAX77705_CHG_REG_DETAILS_02,
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MAX77705_CHG_REG_DTLS_03,
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MAX77705_CHG_REG_CNFG_00,
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MAX77705_CHG_REG_CNFG_01,
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MAX77705_CHG_REG_CNFG_02,
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MAX77705_CHG_REG_CNFG_03,
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MAX77705_CHG_REG_CNFG_04,
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MAX77705_CHG_REG_CNFG_05,
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MAX77705_CHG_REG_CNFG_06,
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MAX77705_CHG_REG_CNFG_07,
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MAX77705_CHG_REG_CNFG_08,
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MAX77705_CHG_REG_CNFG_09,
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MAX77705_CHG_REG_CNFG_10,
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MAX77705_CHG_REG_CNFG_11,
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MAX77705_CHG_REG_CNFG_12,
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MAX77705_CHG_REG_CNFG_13,
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MAX77705_CHG_REG_CNFG_14,
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MAX77705_CHG_REG_SAFEOUT_CTRL
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};
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enum max77705_fuelgauge_reg {
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STATUS_REG = 0x00,
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VALRT_THRESHOLD_REG = 0x01,
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TALRT_THRESHOLD_REG = 0x02,
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SALRT_THRESHOLD_REG = 0x03,
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REMCAP_REP_REG = 0x05,
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SOCREP_REG = 0x06,
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TEMPERATURE_REG = 0x08,
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VCELL_REG = 0x09,
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TIME_TO_EMPTY_REG = 0x11,
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FULLSOCTHR_REG = 0x13,
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CURRENT_REG = 0x0A,
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AVG_CURRENT_REG = 0x0B,
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SOCMIX_REG = 0x0D,
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SOCAV_REG = 0x0E,
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REMCAP_MIX_REG = 0x0F,
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FULLCAP_REG = 0x10,
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RFAST_REG = 0x15,
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AVR_TEMPERATURE_REG = 0x16,
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CYCLES_REG = 0x17,
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DESIGNCAP_REG = 0x18,
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AVR_VCELL_REG = 0x19,
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TIME_TO_FULL_REG = 0x20,
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CONFIG_REG = 0x1D,
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ICHGTERM_REG = 0x1E,
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REMCAP_AV_REG = 0x1F,
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FULLCAP_NOM_REG = 0x23,
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LEARN_CFG_REG = 0x28,
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FILTER_CFG_REG = 0x29,
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MISCCFG_REG = 0x2B,
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QRTABLE20_REG = 0x32,
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FULLCAP_REP_REG = 0x35,
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RCOMP_REG = 0x38,
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VEMPTY_REG = 0x3A,
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FSTAT_REG = 0x3D,
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DISCHARGE_THRESHOLD_REG = 0x40,
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QRTABLE30_REG = 0x42,
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ISYS_REG = 0x43,
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DQACC_REG = 0x45,
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DPACC_REG = 0x46,
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AVGISYS_REG = 0x4B,
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QH_REG = 0x4D,
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VSYS_REG = 0xB1,
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TALRTTH2_REG = 0xB2,
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VBYP_REG = 0xB3,
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CONFIG2_REG = 0xBB,
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IIN_REG = 0xD0,
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OCV_REG = 0xEE,
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VFOCV_REG = 0xFB,
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VFSOC_REG = 0xFF,
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MAX77705_FG_END
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};
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enum max77705_led_reg {
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MAX77705_RGBLED_REG_BASE = 0x30,
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MAX77705_RGBLED_REG_LEDEN = 0,
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MAX77705_RGBLED_REG_LED0BRT,
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MAX77705_RGBLED_REG_LED1BRT,
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MAX77705_RGBLED_REG_LED2BRT,
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MAX77705_RGBLED_REG_LED3BRT,
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MAX77705_RGBLED_REG_LEDRMP,
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MAX77705_RGBLED_REG_LEDBLNK,
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MAX77705_LED_REG_END
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};
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enum max77705_charger_battery_state {
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MAX77705_BATTERY_NOBAT,
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MAX77705_BATTERY_PREQUALIFICATION,
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MAX77705_BATTERY_DEAD,
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MAX77705_BATTERY_GOOD,
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MAX77705_BATTERY_LOWVOLTAGE,
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MAX77705_BATTERY_OVERVOLTAGE,
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MAX77705_BATTERY_RESERVED
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};
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enum max77705_charger_charge_type {
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MAX77705_CHARGER_CONSTANT_CURRENT = 1,
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MAX77705_CHARGER_CONSTANT_VOLTAGE,
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MAX77705_CHARGER_END_OF_CHARGE,
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MAX77705_CHARGER_DONE
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};
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#endif /* __LINUX_MFD_MAX77705_PRIV_H */
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