132 lines
3.2 KiB
C
132 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2024 NXP
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*/
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#ifndef __DC_KMS_H__
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#define __DC_KMS_H__
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#include <linux/completion.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_plane.h>
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#include <drm/drm_vblank.h>
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#include "dc-de.h"
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#include "dc-fu.h"
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#include "dc-pe.h"
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#define DC_CRTC_IRQS 5
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struct dc_crtc_irq {
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struct dc_crtc *dc_crtc;
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unsigned int irq;
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};
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/**
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* struct dc_crtc - DC specific drm_crtc
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*
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* Each display controller contains one content stream and one safety stream.
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* In general, the two streams have the same functionality. One stream is
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* overlaid on the other by @fg. This driver chooses to generate black constant
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* color from the content stream as background color, build plane(s) on the
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* content stream by using layerblend(s) and always generate a constant color
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* from the safety stream. Note that due to the decoupled timing, the safety
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* stream still works to show the constant color properly even when the content
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* stream has completely hung up due to mal-function of this driver.
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*/
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struct dc_crtc {
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/** @base: base drm_crtc structure */
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struct drm_crtc base;
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/** @de: display engine */
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struct dc_de *de;
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/** @cf_cont: content stream constframe */
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struct dc_cf *cf_cont;
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/** @cf_safe: safety stream constframe */
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struct dc_cf *cf_safe;
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/** @ed_cont: content stream extdst */
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struct dc_ed *ed_cont;
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/** @ed_safe: safety stream extdst */
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struct dc_ed *ed_safe;
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/** @fg: framegen */
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struct dc_fg *fg;
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/**
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* @irq_dec_framecomplete:
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*
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* display engine configuration frame complete interrupt
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*/
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unsigned int irq_dec_framecomplete;
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/**
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* @irq_dec_seqcomplete:
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*
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* display engine configuration sequence complete interrupt
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*/
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unsigned int irq_dec_seqcomplete;
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/**
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* @irq_dec_shdload:
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*
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* display engine configuration shadow load interrupt
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*/
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unsigned int irq_dec_shdload;
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/**
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* @irq_ed_cont_shdload:
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*
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* content stream extdst shadow load interrupt
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*/
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unsigned int irq_ed_cont_shdload;
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/**
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* @irq_ed_safe_shdload:
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*
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* safety stream extdst shadow load interrupt
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*/
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unsigned int irq_ed_safe_shdload;
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/**
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* @dec_seqcomplete_done:
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*
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* display engine configuration sequence completion
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*/
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struct completion dec_seqcomplete_done;
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/**
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* @dec_shdload_done:
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*
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* display engine configuration shadow load completion
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*/
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struct completion dec_shdload_done;
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/**
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* @ed_cont_shdload_done:
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*
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* content stream extdst shadow load completion
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*/
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struct completion ed_cont_shdload_done;
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/**
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* @ed_safe_shdload_done:
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*
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* safety stream extdst shadow load completion
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*/
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struct completion ed_safe_shdload_done;
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/** @event: cached pending vblank event */
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struct drm_pending_vblank_event *event;
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/** @irqs: interrupt list */
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struct dc_crtc_irq irqs[DC_CRTC_IRQS];
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};
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/**
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* struct dc_plane - DC specific drm_plane
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*
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* Build a plane on content stream with a fetchunit and a layerblend.
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*/
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struct dc_plane {
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/** @base: base drm_plane structure */
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struct drm_plane base;
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/** @fu: fetchunit */
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struct dc_fu *fu;
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/** @cf: content stream constframe */
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struct dc_cf *cf;
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/** @lb: layerblend */
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struct dc_lb *lb;
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/** @ed: content stream extdst */
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struct dc_ed *ed;
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};
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#endif /* __DC_KMS_H__ */
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