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mirror-linux/arch/riscv/boot/dts/microchip
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Conor Dooley efa310ba00 riscv: dts: microchip: hook up the mpfs' l2cache 
The initial PolarFire SoC devicetree must have been forked off from
the fu540 one prior to the addition of l2cache controller support being
added there. When the controller node was added to mpfs.dtsi, it was
not hooked up to the CPUs & thus sysfs reports an incorrect cache
configuration. Hook it up.

Fixes: 0fa6107eca ("RISC-V: Initial DTS for Microchip ICICLE board")
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
 		2022-07-05 16:54:03 +01:00
..
Makefile riscv: dts: microchip: add the sundance polarberry 2022-06-01 15:28:29 -07:00
mpfs-icicle-kit-fabric.dtsi riscv: dts: microchip: make the fabric dtsi board specific 2022-06-01 15:28:11 -07:00
mpfs-icicle-kit.dts riscv: dts: icicle: sort nodes alphabetically 2022-06-01 15:28:51 -07:00
mpfs-polarberry-fabric.dtsi riscv: dts: microchip: add the sundance polarberry 2022-06-01 15:28:29 -07:00
mpfs-polarberry.dts riscv: dts: microchip: add the sundance polarberry 2022-06-01 15:28:29 -07:00
mpfs.dtsi riscv: dts: microchip: hook up the mpfs' l2cache 2022-07-05 16:54:03 +01:00