9b8e3d4ca0
This change introduces GICv5 load/put. Additionally, it plumbs in save/restore for: * PPIs (ICH_PPI_x_EL2 regs) * ICH_VMCR_EL2 * ICH_APR_EL2 * ICC_ICSR_EL1 A GICv5-specific enable bit is added to struct vgic_vmcr as this differs from previous GICs. On GICv5-native systems, the VMCR only contains the enable bit (driven by the guest via ICC_CR0_EL1.EN) and the priority mask (PCR). A struct gicv5_vpe is also introduced. This currently only contains a single field - bool resident - which is used to track if a VPE is currently running or not, and is used to avoid a case of double load or double put on the WFI path for a vCPU. This struct will be extended as additional GICv5 support is merged, specifically for VPE doorbells. Co-authored-by: Timothy Hayes <timothy.hayes@arm.com> Signed-off-by: Timothy Hayes <timothy.hayes@arm.com> Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Link: https://patch.msgid.link/20260319154937.3619520-18-sascha.bischoff@arm.com Signed-off-by: Marc Zyngier <maz@kernel.org> |
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| .. | ||
| arm-gic-common.h | ||
| arm-gic-v3-prio.h | ||
| arm-gic-v3.h | ||
| arm-gic-v4.h | ||
| arm-gic-v5.h | ||
| arm-gic.h | ||
| arm-vgic-info.h | ||
| arm-vic.h | ||
| chained_irq.h | ||
| irq-bcm2836.h | ||
| irq-madera.h | ||
| irq-msi-lib.h | ||
| irq-omap-intc.h | ||
| irq-renesas-rzt2h.h | ||
| irq-renesas-rzv2h.h | ||
| irq-sa11x0.h | ||
| riscv-aplic.h | ||
| riscv-imsic.h | ||
| xtensa-mx.h | ||
| xtensa-pic.h | ||