Abel Vesa 318b653867 soc: qcom: llcc: Fix slice configuration values for SC8280XP ... commit 77bf4b3ed4 upstream. The slice IDs for CVPFW, CPUSS1 and CPUWHT currently overflow the 32bit LLCC config registers, which means it is writing beyond the upper limit of the ATTR0_CFGn and ATTR1_CFGn range of registers. But the most obvious impact is the fact that the mentioned slices do not get configured at all, which will result in reduced performance. Fix that by using the slice ID values taken from the latest LLCC SC table. Fixes: ec69dfbdc4 ("soc: qcom: llcc: Add sc8180x and sc8280xp configurations") Cc: stable@vger.kernel.org # 5.19+ Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Juerg Haefliger <juerg.haefliger@canonical.com> Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230306135527.509796-1-abel.vesa@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2023-03-30 12:49:29 +02:00
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mediatek	soc: mediatek: mtk-svs: keep svs alive if CONFIG_DEBUG_FS not supported	2023-03-22 13:33:53 +01:00
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qcom	soc: qcom: llcc: Fix slice configuration values for SC8280XP	2023-03-30 12:49:29 +02:00
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