19d9a846d9
Update DT binding for recently introduced TI K3 AM642x SoC [1] which contains 3 port (2 external ports) CPSW3g module. The CPSW3g integrated in MAIN domain and can be configured in multi port or switch modes. The overall functionality and DT bindings are similar to other K3 CPSWxg versions, so DT binding changes are minimal: - reword description - add new compatible 'ti,am642-cpsw-nuss' - allow 2 external ports child nodes - add missed 'assigned-clock' props [1] https://www.ti.com/lit/pdf/spruim2 Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org> |
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| .. | ||
| bindings | ||
| changesets.rst | ||
| dynamic-resolution-notes.rst | ||
| index.rst | ||
| of_unittest.rst | ||
| overlay-notes.rst | ||
| usage-model.rst | ||
| writing-schema.rst | ||