mirror-linux/include/linux/irqchip
Paolo Bonzini 314b40b3b6 KVM/arm64 changes for 6.17, round #1
- Host driver for GICv5, the next generation interrupt controller for
    arm64, including support for interrupt routing, MSIs, interrupt
    translation and wired interrupts.
 
  - Use FEAT_GCIE_LEGACY on GICv5 systems to virtualize GICv3 VMs on
    GICv5 hardware, leveraging the legacy VGIC interface.
 
  - Userspace control of the 'nASSGIcap' GICv3 feature, allowing
    userspace to disable support for SGIs w/o an active state on hardware
    that previously advertised it unconditionally.
 
  - Map supporting endpoints with cacheable memory attributes on systems
    with FEAT_S2FWB and DIC where KVM no longer needs to perform cache
    maintenance on the address range.
 
  - Nested support for FEAT_RAS and FEAT_DoubleFault2, allowing the guest
    hypervisor to inject external aborts into an L2 VM and take traps of
    masked external aborts to the hypervisor.
 
  - Convert more system register sanitization to the config-driven
    implementation.
 
  - Fixes to the visibility of EL2 registers, namely making VGICv3 system
    registers accessible through the VGIC device instead of the ONE_REG
    vCPU ioctls.
 
  - Various cleanups and minor fixes.
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Merge tag 'kvmarm-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD

KVM/arm64 changes for 6.17, round #1

 - Host driver for GICv5, the next generation interrupt controller for
   arm64, including support for interrupt routing, MSIs, interrupt
   translation and wired interrupts.

 - Use FEAT_GCIE_LEGACY on GICv5 systems to virtualize GICv3 VMs on
   GICv5 hardware, leveraging the legacy VGIC interface.

 - Userspace control of the 'nASSGIcap' GICv3 feature, allowing
   userspace to disable support for SGIs w/o an active state on hardware
   that previously advertised it unconditionally.

 - Map supporting endpoints with cacheable memory attributes on systems
   with FEAT_S2FWB and DIC where KVM no longer needs to perform cache
   maintenance on the address range.

 - Nested support for FEAT_RAS and FEAT_DoubleFault2, allowing the guest
   hypervisor to inject external aborts into an L2 VM and take traps of
   masked external aborts to the hypervisor.

 - Convert more system register sanitization to the config-driven
   implementation.

 - Fixes to the visibility of EL2 registers, namely making VGICv3 system
   registers accessible through the VGIC device instead of the ONE_REG
   vCPU ioctls.

 - Various cleanups and minor fixes.
2025-07-29 12:27:40 -04:00
..
arm-gic-common.h
arm-gic-v3-prio.h
arm-gic-v3.h
arm-gic-v4.h KVM: arm64: WARN if unmapping a vLPI fails in any path 2025-06-20 13:52:29 -07:00
arm-gic-v5.h irqchip/gic-v5: Add GICv5 IWB support 2025-07-08 18:35:52 +01:00
arm-gic.h
arm-vgic-info.h irqchip/gic-v5: Populate struct gic_kvm_info 2025-07-08 14:41:06 -07:00
arm-vic.h
chained_irq.h
irq-bcm2836.h
irq-madera.h
irq-msi-lib.h irqchip/irq-msi-lib: Fix build with PCI disabled 2025-07-10 23:46:05 +02:00
irq-omap-intc.h
irq-partition-percpu.h
irq-renesas-rzv2h.h irqchip/renesas-rzv2h: Add rzv2h_icu_register_dma_req() 2025-05-14 15:30:40 +01:00
irq-sa11x0.h
riscv-aplic.h
riscv-imsic.h
xtensa-mx.h
xtensa-pic.h