Maher Sanalla 8d231dbc3b net/mlx5: Expose shared buffer registers bits and structs ... Add the shared receive buffer management and configuration registers: 1. SBPR - Shared Buffer Pools Register 2. SBCM - Shared Buffer Class Management Register Signed-off-by: Maher Sanalla <msanalla@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>		2023-01-10 21:24:39 -08:00
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cq.h	…
device.h	net/mlx5: E-Switch, properly handle ingress tagged packets on VST	2022-12-28 11:38:49 -08:00
doorbell.h	…
driver.h	net/mlx5: Expose shared buffer registers bits and structs	2023-01-10 21:24:39 -08:00
eq.h	…
eswitch.h	…
fs.h	net/mlx5: fs, add match on ranges API	2022-12-08 16:10:53 -08:00
fs_helpers.h	net/mlx5: Remove unused functions	2022-09-27 12:50:27 -07:00
mlx5_ifc.h	net/mlx5: Expose shared buffer registers bits and structs	2023-01-10 21:24:39 -08:00
mlx5_ifc_fpga.h	net/mlx5: Remove from FPGA IFC file not-needed definitions	2022-09-27 12:50:27 -07:00
mlx5_ifc_vdpa.h	…
mpfs.h	…
port.h	…
qp.h	net/mlx5e: xsk: Use KSM for unaligned XSK	2022-09-30 07:55:46 -07:00
rsc_dump.h	…
transobj.h	…
vport.h	net/mlx5: Add generic getters for other functions caps	2022-12-07 20:09:18 -08:00