Xu Yang 048d1a8b9d perf/imx_ddr: don't enable counter0 if none of 4 counters are used ... [ Upstream commit f4e2bd91dd ] In current driver, counter0 will be enabled after ddr_perf_pmu_enable() is called even though none of the 4 counters are used. This will cause counter0 continue to count until ddr_perf_pmu_disabled() is called. If pmu is not disabled all the time, the pmu interrupt will be asserted from time to time due to counter0 will overflow and irq handler will clear it. It's not an expected behavior. This patch will not enable counter0 if none of 4 counters are used. Fixes: 9a66d36cc7 ("drivers/perf: imx_ddr: Add DDR performance counter support to perf") Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230811015438.1999307-2-xu.yang_2@nxp.com Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>		2023-09-13 09:42:29 +02:00
..
hisilicon	drivers/perf: hisi: Don't migrate perf to the CPU going to teardown	2023-07-19 16:21:00 +02:00
Kconfig	…
Makefile	…
alibaba_uncore_drw_pmu.c	…
apple_m1_cpu_pmu.c	…
arm-cci.c	…
arm-ccn.c	…
arm-cmn.c	perf/arm-cmn: Fix DTC reset	2023-07-19 16:21:00 +02:00
arm_dmc620_pmu.c	…
arm_dsu_pmu.c	…
arm_pmu.c	…
arm_pmu_acpi.c	…
arm_pmu_platform.c	…
arm_smmuv3_pmu.c	…
arm_spe_pmu.c	…
fsl_imx8_ddr_perf.c	perf/imx_ddr: don't enable counter0 if none of 4 counters are used	2023-09-13 09:42:29 +02:00
marvell_cn10k_ddr_pmu.c	…
marvell_cn10k_tad_pmu.c	…
qcom_l2_pmu.c	…
qcom_l3_pmu.c	…
riscv_pmu.c	perf: RISC-V: Remove PERF_HES_STOPPED flag checking in riscv_pmu_start()	2023-07-23 13:49:44 +02:00
riscv_pmu_legacy.c	…
riscv_pmu_sbi.c	…
thunderx2_pmu.c	…
xgene_pmu.c	…