SiFive:
Add support for the Eswin EIC7700 SoC, which needs to make sure of the
non-standard cache-ops provided by the ccache driver.
Bindings:
Conversions for two Marvell bindings to yaml, and additions of two
soc-specific compatibles to the axm45mp bindings.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Merge tag 'riscv-cache-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
RISC-V cache drivers for v6.16
SiFive:
Add support for the Eswin EIC7700 SoC, which needs to make sure of the
non-standard cache-ops provided by the ccache driver.
Bindings:
Conversions for two Marvell bindings to yaml, and additions of two
soc-specific compatibles to the axm45mp bindings.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-cache-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
dt-bindings: cache: add QiLai compatible to ax45mp
dt-bindings: cache: Convert marvell,tauros2-cache to DT schema
dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema
dt-bindings: cache: add specific RZ/Five compatible to ax45mp
cache: sifive_ccache: Add ESWIN EIC7700 support
dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility
Link: https://lore.kernel.org/r/20250516-liability-facility-667fc14a2a85@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
07a3c038bd