405 lines
11 KiB
C
405 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek HDMI v2 Display Data Channel Driver
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*
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* Copyright (c) 2021 MediaTek Inc.
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* Copyright (c) 2021 BayLibre, SAS
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* Copyright (c) 2024 Collabora Ltd.
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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#include <drm/drm_edid.h>
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#include "mtk_hdmi_common.h"
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#include "mtk_hdmi_regs_v2.h"
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#define DDC2_DLY_CNT 572 /* BIM=208M/(v*4) = 90Khz */
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#define DDC2_DLY_CNT_EDID 832 /* BIM=208M/(v*4) = 62.5Khz */
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#define SI2C_ADDR_READ 0xf4
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#define SCDC_I2C_SLAVE_ADDRESS 0x54
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struct mtk_hdmi_ddc {
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struct device *dev;
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struct regmap *regs;
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struct clk *clk;
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struct i2c_adapter adap;
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};
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static int mtk_ddc_check_and_rise_low_bus(struct mtk_hdmi_ddc *ddc)
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{
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u32 val;
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regmap_read(ddc->regs, HDCP2X_DDCM_STATUS, &val);
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if (val & DDC_I2C_BUS_LOW) {
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regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
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FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLOCK_SCL));
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usleep_range(250, 300);
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}
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if (val & DDC_I2C_NO_ACK) {
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u32 ddc_ctrl, hpd_ddc_ctrl, hpd_ddc_status;
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regmap_read(ddc->regs, DDC_CTRL, &ddc_ctrl);
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regmap_read(ddc->regs, HPD_DDC_CTRL, &hpd_ddc_ctrl);
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regmap_read(ddc->regs, HPD_DDC_STATUS, &hpd_ddc_status);
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}
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if (val & DDC_I2C_NO_ACK)
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return -EIO;
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return 0;
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}
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static int mtk_ddcm_write_hdmi(struct mtk_hdmi_ddc *ddc, u16 addr_id,
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u16 offset_id, u16 data_cnt, u8 *wr_data)
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{
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u32 val;
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int ret, i;
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/* Don't allow transfer with a size over than the transfer fifo size
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* (16 byte)
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*/
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if (data_cnt > 16) {
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dev_err(ddc->dev, "Invalid DDCM write request\n");
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return -EINVAL;
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}
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/* If down, rise bus for write operation */
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mtk_ddc_check_and_rise_low_bus(ddc);
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regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,
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FIELD_PREP(HPD_DDC_DELAY_CNT, DDC2_DLY_CNT));
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/* In case there is no payload data, just do a single write for the
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* address only
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*/
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if (wr_data) {
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/* Fill transfer fifo with payload data */
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for (i = 0; i < data_cnt; i++) {
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regmap_write(ddc->regs, SI2C_CTRL,
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FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
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FIELD_PREP(SI2C_WDATA, wr_data[i]) |
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SI2C_WR);
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}
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}
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regmap_write(ddc->regs, DDC_CTRL,
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FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_WRITE) |
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FIELD_PREP(DDC_CTRL_DIN_CNT, wr_data == NULL ? 0 : data_cnt) |
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FIELD_PREP(DDC_CTRL_OFFSET, offset_id) |
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FIELD_PREP(DDC_CTRL_ADDR, addr_id));
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usleep_range(1000, 1250);
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ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,
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!(val & DDC_I2C_IN_PROG), 500, 1000);
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if (ret) {
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dev_err(ddc->dev, "DDC I2C write timeout\n");
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/* Abort transfer if it is still in progress */
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regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
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FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ABORT_XFER));
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return ret;
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}
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/* The I2C bus might be down after WR operation: rise it again */
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ret = mtk_ddc_check_and_rise_low_bus(ddc);
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if (ret) {
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dev_err(ddc->dev, "Error during write operation: No ACK\n");
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return ret;
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}
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return 0;
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}
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static int mtk_ddcm_read_hdmi(struct mtk_hdmi_ddc *ddc, u16 uc_dev,
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u8 addr, u8 *puc_value, u16 data_cnt)
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{
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u16 dly_cnt, i, uc_idx;
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u32 rem, temp_length, uc_read_count, val;
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u64 loop_counter;
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int ret;
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mtk_ddc_check_and_rise_low_bus(ddc);
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regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
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FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLEAR_FIFO));
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if (data_cnt >= 16) {
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temp_length = 16;
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loop_counter = data_cnt;
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rem = do_div(loop_counter, temp_length);
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if (rem)
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loop_counter++;
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} else {
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temp_length = data_cnt;
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loop_counter = 1;
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}
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if (uc_dev >= DDC_ADDR)
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dly_cnt = DDC2_DLY_CNT_EDID;
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else
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dly_cnt = DDC2_DLY_CNT;
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regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,
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FIELD_PREP(HPD_DDC_DELAY_CNT, dly_cnt));
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for (i = 0; i < loop_counter; i++) {
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rem = data_cnt % 16;
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if (i > 0 && i == (loop_counter - 1) && rem)
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temp_length = rem;
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/* 0x51 - 0x53: Flow control */
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if (uc_dev > DDC_ADDR && uc_dev <= 0x53) {
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regmap_update_bits(ddc->regs, SCDC_CTRL, SCDC_DDC_SEGMENT,
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FIELD_PREP(SCDC_DDC_SEGMENT, uc_dev - DDC_ADDR));
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regmap_write(ddc->regs, DDC_CTRL,
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FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ENH_READ_NOACK) |
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FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) |
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FIELD_PREP(DDC_CTRL_OFFSET, addr + i * temp_length) |
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FIELD_PREP(DDC_CTRL_ADDR, DDC_ADDR));
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} else {
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u16 offset;
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if (addr != 0x43)
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offset = i * 16;
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else
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offset = 0;
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regmap_write(ddc->regs, DDC_CTRL,
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FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_READ_NOACK) |
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FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) |
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FIELD_PREP(DDC_CTRL_OFFSET, addr + offset) |
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FIELD_PREP(DDC_CTRL_ADDR, uc_dev));
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}
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usleep_range(5000, 5500);
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ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,
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!(val & DDC_I2C_IN_PROG), 1000,
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500 * (temp_length + 5));
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if (ret) {
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dev_err(ddc->dev, "Timeout waiting for DDC I2C\n");
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/* Abort transfer if it is still in progress */
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regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
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FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ABORT_XFER));
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return ret;
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}
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ret = mtk_ddc_check_and_rise_low_bus(ddc);
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if (ret) {
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dev_err(ddc->dev, "Error during read operation: No ACK\n");
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return ret;
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}
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for (uc_idx = 0; uc_idx < temp_length; uc_idx++) {
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unsigned int read_idx = i * 16 + uc_idx;
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regmap_write(ddc->regs, SI2C_CTRL,
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FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
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SI2C_RD);
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regmap_read(ddc->regs, HPD_DDC_STATUS, &val);
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puc_value[read_idx] = FIELD_GET(DDC_DATA_OUT, val);
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regmap_write(ddc->regs, SI2C_CTRL,
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FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
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SI2C_CONFIRM_READ);
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/*
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* If HDMI IP gets reset during EDID read, DDC read
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* operation will fail and its delay counter will be
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* reset to 400.
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*/
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regmap_read(ddc->regs, HPD_DDC_CTRL, &val);
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if (FIELD_GET(HPD_DDC_DELAY_CNT, val) < DDC2_DLY_CNT)
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return 0;
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uc_read_count = read_idx + 1;
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}
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}
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if (uc_read_count > U8_MAX)
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dev_warn(ddc->dev, "Invalid read data count %u\n", uc_read_count);
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return uc_read_count;
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}
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static int mtk_hdmi_fg_ddc_data_read(struct mtk_hdmi_ddc *ddc, u16 b_dev,
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u8 data_addr, u16 data_cnt, u8 *pr_data)
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{
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int read_data_cnt;
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u16 req_data_cnt;
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if (!data_cnt) {
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dev_err(ddc->dev, "Invalid DDCM read request\n");
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return -EINVAL;
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}
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req_data_cnt = U8_MAX - data_addr + 1;
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if (req_data_cnt > data_cnt)
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req_data_cnt = data_cnt;
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regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);
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read_data_cnt = mtk_ddcm_read_hdmi(ddc, b_dev, data_addr, pr_data, req_data_cnt);
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if (read_data_cnt < 0)
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return read_data_cnt;
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else if (read_data_cnt != req_data_cnt)
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return -EINVAL;
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return 0;
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}
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static int mtk_hdmi_ddc_fg_data_write(struct mtk_hdmi_ddc *ddc, u16 b_dev,
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u8 data_addr, u16 data_cnt, u8 *pr_data)
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{
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regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);
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return mtk_ddcm_write_hdmi(ddc, b_dev, data_addr, data_cnt, pr_data);
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}
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static int mtk_hdmi_ddc_v2_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
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{
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struct mtk_hdmi_ddc *ddc;
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u8 offset = 0;
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int i, ret;
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ddc = adapter->algo_data;
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for (i = 0; i < num; i++) {
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struct i2c_msg *msg = &msgs[i];
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if (!msg->buf) {
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dev_err(ddc->dev, "No message buffer\n");
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return -EINVAL;
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}
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if (msg->flags & I2C_M_RD) {
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/*
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* The underlying DDC hardware always issues a write request
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* that assigns the read offset as part of the read operation,
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* therefore, use the `offset` value assigned in the previous
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* write request from drm_edid
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*/
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ret = mtk_hdmi_fg_ddc_data_read(ddc, msg->addr, offset,
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msg->len, &msg->buf[0]);
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if (ret)
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return ret;
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} else {
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/*
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* The HW needs the data offset, found in buf[0], in the
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* DDC_CTRL register, and each byte of data, starting at
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* buf[1], goes in the SI2C_WDATA register.
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*/
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ret = mtk_hdmi_ddc_fg_data_write(ddc, msg->addr, msg->buf[0],
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msg->len - 1, &msg->buf[1]);
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if (ret)
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return ret;
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/*
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* Store the offset value requested by drm_edid or by
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* scdc to use in subsequent read requests.
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*/
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if ((msg->addr == DDC_ADDR || msg->addr == SCDC_I2C_SLAVE_ADDRESS) &&
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msg->len == 1) {
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offset = msg->buf[0];
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}
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}
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}
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return i;
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}
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static u32 mtk_hdmi_ddc_v2_func(struct i2c_adapter *adapter)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm mtk_hdmi_ddc_v2_algorithm = {
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.master_xfer = mtk_hdmi_ddc_v2_xfer,
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.functionality = mtk_hdmi_ddc_v2_func,
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};
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static int mtk_hdmi_ddc_v2_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mtk_hdmi_ddc *ddc;
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int ret;
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ddc = devm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL);
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if (!ddc)
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return -ENOMEM;
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ddc->dev = dev;
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ddc->regs = device_node_to_regmap(dev->parent->of_node);
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if (IS_ERR_OR_NULL(ddc->regs))
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return dev_err_probe(dev,
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IS_ERR(ddc->regs) ? PTR_ERR(ddc->regs) : -EINVAL,
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"Cannot get regmap\n");
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ddc->clk = devm_clk_get_enabled(dev, NULL);
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if (IS_ERR(ddc->clk))
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return dev_err_probe(dev, PTR_ERR(ddc->clk), "Cannot get DDC clock\n");
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strscpy(ddc->adap.name, "mediatek-hdmi-ddc-v2", sizeof(ddc->adap.name));
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ddc->adap.owner = THIS_MODULE;
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ddc->adap.algo = &mtk_hdmi_ddc_v2_algorithm;
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ddc->adap.retries = 3;
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ddc->adap.dev.of_node = dev->of_node;
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ddc->adap.algo_data = ddc;
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ddc->adap.dev.parent = &pdev->dev;
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ret = devm_pm_runtime_enable(&pdev->dev);
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if (ret)
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return dev_err_probe(&pdev->dev, ret, "Cannot enable Runtime PM\n");
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pm_runtime_get_sync(dev);
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ret = devm_i2c_add_adapter(dev, &ddc->adap);
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if (ret < 0)
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return dev_err_probe(dev, ret, "Cannot add DDC I2C adapter\n");
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platform_set_drvdata(pdev, ddc);
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return 0;
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}
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static const struct of_device_id mtk_hdmi_ddc_v2_match[] = {
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{ .compatible = "mediatek,mt8195-hdmi-ddc" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, mtk_hdmi_ddc_v2_match);
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static struct platform_driver mtk_hdmi_ddc_v2_driver = {
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.probe = mtk_hdmi_ddc_v2_probe,
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.driver = {
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.name = "mediatek-hdmi-ddc-v2",
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.of_match_table = mtk_hdmi_ddc_v2_match,
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},
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};
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module_platform_driver(mtk_hdmi_ddc_v2_driver);
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MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
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MODULE_AUTHOR("Can Zeng <can.zeng@mediatek.com>");
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MODULE_DESCRIPTION("MediaTek HDMIv2 DDC Driver");
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MODULE_LICENSE("GPL");
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