e7a8386941
A100 features an updated DPHY, which moves PLL control inside the DPHY register space. (Previously PLL-MIPI was controlled from the CCU. This does not affect the "clocks" property because the link between PLL-MIPI and the DPHY was never represented in the devicetree.) It also requires a modified analog power-on sequence. Finally, the new DPHY adds support for operating as an LVDS PHY. D1 uses this same variant. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221114022113.31694-5-samuel@sholland.org Signed-off-by: Vinod Koul <vkoul@kernel.org> |
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| .. | ||
| bindings | ||
| changesets.rst | ||
| dynamic-resolution-notes.rst | ||
| index.rst | ||
| kernel-api.rst | ||
| of_unittest.rst | ||
| overlay-notes.rst | ||
| usage-model.rst | ||