63 lines
2.1 KiB
C
63 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2025, Collabora Ltd.
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*/
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#ifndef _LINUX_HW_BITFIELD_H
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#define _LINUX_HW_BITFIELD_H
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#include <linux/bitfield.h>
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#include <linux/build_bug.h>
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#include <linux/limits.h>
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/**
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* FIELD_PREP_WM16() - prepare a bitfield element with a mask in the upper half
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* @_mask: shifted mask defining the field's length and position
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* @_val: value to put in the field
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*
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* FIELD_PREP_WM16() masks and shifts up the value, as well as bitwise ORs the
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* result with the mask shifted up by 16.
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*
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* This is useful for a common design of hardware registers where the upper
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* 16-bit half of a 32-bit register is used as a write-enable mask. In such a
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* register, a bit in the lower half is only updated if the corresponding bit
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* in the upper half is high.
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*/
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#define FIELD_PREP_WM16(_mask, _val) \
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({ \
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typeof(_val) __val = _val; \
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typeof(_mask) __mask = _mask; \
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__BF_FIELD_CHECK(__mask, ((u16)0U), __val, \
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"HWORD_UPDATE: "); \
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(((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) | \
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((__mask) << 16); \
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})
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/**
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* FIELD_PREP_WM16_CONST() - prepare a constant bitfield element with a mask in
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* the upper half
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* @_mask: shifted mask defining the field's length and position
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* @_val: value to put in the field
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*
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* FIELD_PREP_WM16_CONST() masks and shifts up the value, as well as bitwise ORs
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* the result with the mask shifted up by 16.
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*
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* This is useful for a common design of hardware registers where the upper
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* 16-bit half of a 32-bit register is used as a write-enable mask. In such a
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* register, a bit in the lower half is only updated if the corresponding bit
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* in the upper half is high.
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*
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* Unlike FIELD_PREP_WM16(), this is a constant expression and can therefore
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* be used in initializers. Error checking is less comfortable for this
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* version.
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*/
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#define FIELD_PREP_WM16_CONST(_mask, _val) \
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( \
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FIELD_PREP_CONST(_mask, _val) | \
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(BUILD_BUG_ON_ZERO(const_true((u64)(_mask) > U16_MAX)) + \
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((_mask) << 16)) \
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)
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#endif /* _LINUX_HW_BITFIELD_H */
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