113 lines
2.5 KiB
YAML
113 lines
2.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Neural Processing Unit IP from Rockchip
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maintainers:
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- Tomeu Vizoso <tomeu@tomeuvizoso.net>
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description:
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Rockchip IP for accelerating inference of neural networks.
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There is to be a node per each NPU core in the SoC, and each core should reference all the
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resources that it needs to function, such as clocks, power domains, and resets.
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properties:
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$nodename:
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pattern: '^npu@[a-f0-9]+$'
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compatible:
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enum:
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- rockchip,rk3588-rknn-core
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: pc # Program Control-related registers
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- const: cna # Convolution Neural Network Accelerator registers
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- const: core # Main NPU core processing unit registers
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: aclk
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- const: hclk
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- const: npu
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- const: pclk
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interrupts:
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maxItems: 1
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iommus:
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maxItems: 1
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npu-supply: true
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power-domains:
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maxItems: 1
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: srst_a
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- const: srst_h
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sram-supply: true
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- interrupts
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- iommus
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- power-domains
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- resets
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- reset-names
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- npu-supply
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- sram-supply
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rockchip,rk3588-cru.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/rk3588-power.h>
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#include <dt-bindings/reset/rockchip,rk3588-cru.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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npu@fdab0000 {
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compatible = "rockchip,rk3588-rknn-core";
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reg = <0x0 0xfdab0000 0x0 0x1000>,
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<0x0 0xfdab1000 0x0 0x1000>,
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<0x0 0xfdab3000 0x0 0x1000>;
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reg-names = "pc", "cna", "core";
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clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>,
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<&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
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clock-names = "aclk", "hclk", "npu", "pclk";
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
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iommus = <&rknn_mmu_0>;
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npu-supply = <&vdd_npu_s0>;
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power-domains = <&power RK3588_PD_NPUTOP>;
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resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>;
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reset-names = "srst_a", "srst_h";
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sram-supply = <&vdd_npu_mem_s0>;
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};
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};
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...
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