695949d8b1
The GICv5 architecture implements the Interrupt Wire Bridge (IWB) in order to support wired interrupts that cannot be connected directly to an IRS and instead uses the ITS to translate a wire event into an IRQ signal. Add the wired-to-MSI IWB driver to manage IWB wired interrupts. An IWB is connected to an ITS and it has its own deviceID for all interrupt wires that it manages; the IWB input wire number must be exposed to the ITS as an eventID with a 1:1 mapping. This eventID is not programmable and therefore requires a new msi_alloc_info_t flag to make sure the ITS driver does not allocate an eventid for the wire but rather it uses the msi_alloc_info_t.hwirq number to gather the ITS eventID. Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com> Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Co-developed-by: Timothy Hayes <timothy.hayes@arm.com> Signed-off-by: Timothy Hayes <timothy.hayes@arm.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Marc Zyngier <maz@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-29-12e71f1b3528@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org> |
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| .. | ||
| arm-gic-common.h | ||
| arm-gic-v3-prio.h | ||
| arm-gic-v3.h | ||
| arm-gic-v4.h | ||
| arm-gic-v5.h | ||
| arm-gic.h | ||
| arm-vgic-info.h | ||
| arm-vic.h | ||
| chained_irq.h | ||
| irq-bcm2836.h | ||
| irq-madera.h | ||
| irq-msi-lib.h | ||
| irq-omap-intc.h | ||
| irq-partition-percpu.h | ||
| irq-renesas-rzv2h.h | ||
| irq-sa11x0.h | ||
| riscv-aplic.h | ||
| riscv-imsic.h | ||
| xtensa-mx.h | ||
| xtensa-pic.h | ||