Wayne Chang b246caa680 phy: tegra: xusb: Explicitly configure HS_DISCON_LEVEL to 0x7 ... The USB2 Bias Pad Control register manages analog parameters for signal detection. Previously, the HS_DISCON_LEVEL relied on hardware reset values, which may lead to the detection failure. Explicitly configure HS_DISCON_LEVEL to 0x7. This ensures the disconnect threshold is sufficient to guarantee reliable detection. Fixes: bbf711682c ("phy: tegra: xusb: Add Tegra186 support") Cc: stable@vger.kernel.org Signed-off-by: Wayne Chang <waynec@nvidia.com> Link: https://patch.msgid.link/20251212032116.768307-1-waynec@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2025-12-24 12:37:27 +05:30
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Kconfig	phy: tegra: p2u: Broaden architecture dependency	2025-05-14 12:28:04 +01:00
Makefile	phy: tegra: xusb: Add Tegra234 support	2023-01-12 22:57:06 +05:30
phy-tegra194-p2u.c	phy: Explicitly include correct DT includes	2023-07-17 11:52:56 +05:30
xusb-tegra124.c	phy: tegra: xusb: Remove usb3 supply	2022-11-07 10:20:25 +05:30
xusb-tegra186.c	phy: tegra: xusb: Explicitly configure HS_DISCON_LEVEL to 0x7	2025-12-24 12:37:27 +05:30
xusb-tegra210.c	phy: tegra: xusb: fix device and OF node leak at probe	2025-08-12 21:30:00 +05:30
xusb.c	phy: Fix error handling in tegra_xusb_port_init	2025-05-14 12:28:43 +01:00
xusb.h	phy: tegra: xusb: Decouple CYA_TRK_CODE_UPDATE_ON_IDLE from trk_hw_mode	2025-06-15 19:46:01 +05:30