Fudong Wang b23c96589f drm/amd/display: Add smu write msg id fail retry process ... commit 72105dcfa3 upstream. A benchmark stress test (12-40 machines x 48hours) found that DCN315 has cases where DC writes to an indirect register to set the smu clock msg id, but when we go to read the same indirect register the returned msg id doesn't match with what we just set it to. So, to fix this retry the write until the register's value matches with the requested value. Cc: stable@vger.kernel.org # 6.1+ Fixes: f949039961 ("drm/amd/display: Add DCN315 CLK_MGR") Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Fudong Wang <fudong.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2023-09-13 09:43:02 +02:00
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drm	drm/amd/display: Add smu write msg id fail retry process	2023-09-13 09:43:02 +02:00
host1x	gpu: host1x: Fix memory leak of device names	2023-05-11 23:03:12 +09:00
ipu-v3	gpu: ipu-v3: common: Add of_node_put() for reference returned by of_graph_get_port_by_id()	2023-03-10 09:33:10 +01:00
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