Victor Lu 8b22f04833 drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts for vega20_ih ... Port this change to vega20_ih.c: commit afbf7955ff ("drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts") Original commit message: "Why: Setting IH_RB_WPTR register to 0 will not clear the RB_OVERFLOW bit if RB_ENABLE is not set. How to fix: Set WPTR_OVERFLOW_CLEAR bit after RB_ENABLE bit is set. The RB_ENABLE bit is required to be set, together with WPTR_OVERFLOW_ENABLE bit so that setting WPTR_OVERFLOW_CLEAR bit would clear the RB_OVERFLOW." Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2024-10-22 17:50:40 -04:00
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acp	drivers/gpu: Fix misalignment in comment block	2024-05-29 14:48:30 -04:00
amdgpu	drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts for vega20_ih	2024-10-22 17:50:40 -04:00
amdkfd	drm/amdkfd: fix the hang caused by the write reorder to fence_addr	2024-10-22 17:50:39 -04:00
amdxcp	drm/amd/amdxcp: Fix warnings	2024-05-08 15:17:05 -04:00
display	drm/amdgpu: Clean the functions pointer set as NULL	2024-10-22 17:50:39 -04:00
include	drm/amdgpu: init saw registers for mmhub v1.0	2024-10-22 17:49:38 -04:00
pm	drm/amdgpu: Clean the functions pointer set as NULL	2024-10-22 17:50:39 -04:00