2fdfc1bb75
Update phy driver to enable SS combo phy for this SoC. New registers' definitions, phy ops (init/exit), and dedicated phy driver data structure are added for SS combo phy. Add these changes in the driver to support SS combo phy for this SoC. Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com> Link: https://patch.msgid.link/20251124110453.2887437-7-pritam.sutar@samsung.com Signed-off-by: Vinod Koul <vkoul@kernel.org> |
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| .. | ||
| exynos-chipid.h | ||
| exynos-pmu.h | ||
| exynos-regs-pmu.h | ||
| s3c-pm.h | ||