194 lines
6.2 KiB
C
194 lines
6.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Maxim MAX77705 definitions.
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*
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* Copyright (C) 2015 Samsung Electronics, Inc.
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* Copyright (C) 2025 Dzmitry Sankouski <dsankouski@gmail.com>
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*/
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#ifndef __MAX77705_CHARGER_H
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#define __MAX77705_CHARGER_H __FILE__
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#include <linux/regmap.h>
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/* MAX77705_CHG_REG_CHG_INT */
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#define MAX77705_BYP_I (0)
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#define MAX77705_INP_LIMIT_I (1)
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#define MAX77705_BATP_I (2)
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#define MAX77705_BAT_I (3)
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#define MAX77705_CHG_I (4)
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#define MAX77705_WCIN_I (5)
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#define MAX77705_CHGIN_I (6)
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#define MAX77705_AICL_I (7)
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/* MAX77705_CHG_REG_CHG_INT_OK */
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#define MAX77705_BYP_OK BIT(MAX77705_BYP_I)
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#define MAX77705_DISQBAT_OK BIT(MAX77705_INP_LIMIT_I)
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#define MAX77705_BATP_OK BIT(MAX77705_BATP_I)
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#define MAX77705_BAT_OK BIT(MAX77705_BAT_I)
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#define MAX77705_CHG_OK BIT(MAX77705_CHG_I)
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#define MAX77705_WCIN_OK BIT(MAX77705_WCIN_I)
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#define MAX77705_CHGIN_OK BIT(MAX77705_CHGIN_I)
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#define MAX77705_AICL_OK BIT(MAX77705_AICL_I)
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/* MAX77705_CHG_REG_DETAILS_00 */
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#define MAX77705_BATP_DTLS BIT(0)
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#define MAX77705_WCIN_DTLS GENMASK(4, 3)
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#define MAX77705_WCIN_DTLS_SHIFT 3
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#define MAX77705_CHGIN_DTLS GENMASK(6, 5)
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#define MAX77705_CHGIN_DTLS_SHIFT 5
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/* MAX77705_CHG_REG_DETAILS_01 */
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#define MAX77705_CHG_DTLS GENMASK(3, 0)
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#define MAX77705_CHG_DTLS_SHIFT 0
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#define MAX77705_BAT_DTLS GENMASK(6, 4)
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#define MAX77705_BAT_DTLS_SHIFT 4
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/* MAX77705_CHG_REG_DETAILS_02 */
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#define MAX77705_BYP_DTLS GENMASK(3, 0)
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#define MAX77705_BYP_DTLS_SHIFT 0
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/* MAX77705_CHG_REG_CNFG_00 */
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#define MAX77705_CHG_SHIFT 0
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#define MAX77705_UNO_SHIFT 1
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#define MAX77705_OTG_SHIFT 1
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#define MAX77705_BUCK_SHIFT 2
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#define MAX77705_BOOST_SHIFT 3
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#define MAX77705_WDTEN_SHIFT 4
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#define MAX77705_CHG_MASK BIT(MAX77705_CHG_SHIFT)
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#define MAX77705_UNO_MASK BIT(MAX77705_UNO_SHIFT)
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#define MAX77705_OTG_MASK BIT(MAX77705_OTG_SHIFT)
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#define MAX77705_BUCK_MASK BIT(MAX77705_BUCK_SHIFT)
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#define MAX77705_BOOST_MASK BIT(MAX77705_BOOST_SHIFT)
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#define MAX77705_WDTEN_MASK BIT(MAX77705_WDTEN_SHIFT)
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#define MAX77705_UNO_CTRL (MAX77705_UNO_MASK | MAX77705_BOOST_MASK)
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#define MAX77705_OTG_CTRL (MAX77705_OTG_MASK | MAX77705_BOOST_MASK)
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/* MAX77705_CHG_REG_CNFG_01 */
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#define MAX77705_FCHGTIME_DISABLE 0
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#define MAX77705_CHG_RSTRT_DISABLE 0x3
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#define MAX77705_CHG_PQEN_DISABLE 0
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#define MAX77705_CHG_PQEN_ENABLE 1
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/* MAX77705_CHG_REG_CNFG_02 */
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#define MAX77705_OTG_ILIM_500 0
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#define MAX77705_OTG_ILIM_900 1
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#define MAX77705_OTG_ILIM_1200 2
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#define MAX77705_OTG_ILIM_1500 3
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/* MAX77705_CHG_REG_CNFG_03 */
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#define MAX77705_TO_ITH_150MA 0
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#define MAX77705_TO_TIME_30M 3
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#define MAX77705_SYS_TRACK_ENABLE 0
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#define MAX77705_SYS_TRACK_DISABLE 1
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/* MAX77705_CHG_REG_CNFG_04 */
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#define MAX77705_CHG_MINVSYS_SHIFT 6
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#define MAX77705_CHG_MINVSYS_MASK GENMASK(7, 6)
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/* MAX77705_CHG_REG_CNFG_05 */
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#define MAX77705_B2SOVRC_DISABLE 0
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#define MAX77705_B2SOVRC_4_5A 6
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#define MAX77705_B2SOVRC_4_8A 8
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#define MAX77705_B2SOVRC_5_0A 9
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/* MAX77705_CHG_CNFG_06 */
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#define MAX77705_WDTCLR_SHIFT 0
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#define MAX77705_WDTCLR_MASK GENMASK(1, 0)
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#define MAX77705_WDTCLR 1
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#define MAX77705_CHGPROT_UNLOCKED 3
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#define MAX77705_SLOWEST_LX_SLOPE 3
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/* MAX77705_CHG_REG_CNFG_07 */
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#define MAX77705_CHG_FMBST 4
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#define MAX77705_REG_FMBST_SHIFT 2
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#define MAX77705_REG_FMBST_MASK BIT(MAX77705_REG_FMBST_SHIFT)
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#define MAX77705_REG_FGSRC_SHIFT 1
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#define MAX77705_REG_FGSRC_MASK BIT(MAX77705_REG_FGSRC_SHIFT)
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/* MAX77705_CHG_REG_CNFG_08 */
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#define MAX77705_CHG_FSW_3MHz 0
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#define MAX77705_CHG_FSW_2MHz 1
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#define MAX77705_CHG_FSW_1_5MHz 2
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/* MAX77705_CHG_REG_CNFG_09 */
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#define MAX77705_CHG_DISABLE 0
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/* MAX77705_CHG_REG_CNFG_12 */
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/* REG=4.5V, UVLO=4.7V */
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#define MAX77705_VCHGIN_4_5 0
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/* REG=4.5V, UVLO=4.7V */
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#define MAX77705_WCIN_4_5 0
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#define MAX77705_DISABLE_SKIP 1
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#define MAX77705_AUTO_SKIP 0
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#define AICL_WORK_DELAY_MS 100
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/* uA */
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#define MAX77705_CURRENT_CHGIN_STEP 25000
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#define MAX77705_CURRENT_CHG_STEP 50000
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#define MAX77705_CURRENT_CHGIN_MIN 100000
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#define MAX77705_CURRENT_CHGIN_MAX 3200000
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enum max77705_field_idx {
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MAX77705_CHGPROT,
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MAX77705_CHG_EN,
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MAX77705_CHG_CC_LIM,
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MAX77705_CHG_CHGIN_LIM,
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MAX77705_CHG_CV_PRM,
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MAX77705_CHG_PQEN,
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MAX77705_CHG_RSTRT,
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MAX77705_CHG_WCIN,
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MAX77705_FCHGTIME,
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MAX77705_LX_SLOPE,
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MAX77705_MODE,
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MAX77705_OTG_ILIM,
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MAX77705_REG_B2SOVRC,
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MAX77705_REG_DISKIP,
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MAX77705_REG_FSW,
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MAX77705_SYS_TRACK,
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MAX77705_TO,
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MAX77705_TO_TIME,
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MAX77705_VBYPSET,
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MAX77705_VCHGIN,
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MAX77705_WCIN,
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MAX77705_N_REGMAP_FIELDS,
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};
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static const struct reg_field max77705_reg_field[MAX77705_N_REGMAP_FIELDS] = {
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[MAX77705_MODE] = REG_FIELD(MAX77705_CHG_REG_CNFG_00, 0, 3),
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[MAX77705_FCHGTIME] = REG_FIELD(MAX77705_CHG_REG_CNFG_01, 0, 2),
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[MAX77705_CHG_RSTRT] = REG_FIELD(MAX77705_CHG_REG_CNFG_01, 4, 5),
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[MAX77705_CHG_PQEN] = REG_FIELD(MAX77705_CHG_REG_CNFG_01, 7, 7),
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[MAX77705_CHG_CC_LIM] = REG_FIELD(MAX77705_CHG_REG_CNFG_02, 0, 5),
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[MAX77705_OTG_ILIM] = REG_FIELD(MAX77705_CHG_REG_CNFG_02, 6, 7),
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[MAX77705_TO] = REG_FIELD(MAX77705_CHG_REG_CNFG_03, 0, 2),
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[MAX77705_TO_TIME] = REG_FIELD(MAX77705_CHG_REG_CNFG_03, 3, 5),
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[MAX77705_SYS_TRACK] = REG_FIELD(MAX77705_CHG_REG_CNFG_03, 7, 7),
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[MAX77705_CHG_CV_PRM] = REG_FIELD(MAX77705_CHG_REG_CNFG_04, 0, 5),
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[MAX77705_REG_B2SOVRC] = REG_FIELD(MAX77705_CHG_REG_CNFG_05, 0, 3),
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[MAX77705_CHGPROT] = REG_FIELD(MAX77705_CHG_REG_CNFG_06, 2, 3),
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[MAX77705_LX_SLOPE] = REG_FIELD(MAX77705_CHG_REG_CNFG_06, 5, 6),
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[MAX77705_REG_FSW] = REG_FIELD(MAX77705_CHG_REG_CNFG_08, 0, 1),
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[MAX77705_CHG_CHGIN_LIM] = REG_FIELD(MAX77705_CHG_REG_CNFG_09, 0, 6),
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[MAX77705_CHG_EN] = REG_FIELD(MAX77705_CHG_REG_CNFG_09, 7, 7),
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[MAX77705_CHG_WCIN] = REG_FIELD(MAX77705_CHG_REG_CNFG_10, 0, 5),
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[MAX77705_VBYPSET] = REG_FIELD(MAX77705_CHG_REG_CNFG_11, 0, 6),
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[MAX77705_REG_DISKIP] = REG_FIELD(MAX77705_CHG_REG_CNFG_12, 0, 0),
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[MAX77705_WCIN] = REG_FIELD(MAX77705_CHG_REG_CNFG_12, 1, 2),
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[MAX77705_VCHGIN] = REG_FIELD(MAX77705_CHG_REG_CNFG_12, 3, 4),
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};
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struct max77705_charger_data {
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struct device *dev;
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struct regmap *regmap;
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struct regmap_field *rfield[MAX77705_N_REGMAP_FIELDS];
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struct power_supply_battery_info *bat_info;
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struct workqueue_struct *wqueue;
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struct work_struct chgin_work;
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struct power_supply *psy_chg;
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};
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#endif /* __MAX77705_CHARGER_H */
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