d170e938f0
[Description] - On init if a display is connected, we need to maintain the DISPCLK frequency - Even though DPG_EN=1, the display still requires the correct timing or it could cause audio corruption (if DISPCLK freq is reduced) - Read the current DISPCLK freq and request the same value to ensure the timing is valid and unchanged - However, add option to do a full pipe power down (including link) which will also avoid audio related issues - Disabled for the time being on dcn32 Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
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| .. | ||
| hw | ||
| bw_fixed.h | ||
| clock_source.h | ||
| compressor.h | ||
| core_status.h | ||
| core_types.h | ||
| custom_float.h | ||
| dce_calcs.h | ||
| dcn_calc_math.h | ||
| dcn_calcs.h | ||
| hw_sequencer.h | ||
| hw_sequencer_private.h | ||
| link.h | ||
| link_enc_cfg.h | ||
| link_hwss.h | ||
| reg_helper.h | ||
| resource.h | ||
| vm_helper.h | ||