10f338bd0a
The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs. We have implemented LiteX support for a couple of opensource MIPS CPU cores including microAptiv UP from MIPS, GS232 from Loongson, and CDIM from CQU. For this platform, devicetree is generated by litex python scripts so there is no devicetree addition necessary. Link: https://github.com/enjoy-digital/litex/pull/1990 Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> |
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| .. | ||
| 32r1.config | ||
| 32r2.config | ||
| 32r6.config | ||
| 64r1.config | ||
| 64r2.config | ||
| 64r6.config | ||
| board-boston.config | ||
| board-litex.config | ||
| board-marduk.config | ||
| board-ni169445.config | ||
| board-ocelot.config | ||
| board-ranchu.config | ||
| board-sead-3.config | ||
| board-virt.config | ||
| board-xilfpga.config | ||
| eb.config | ||
| el.config | ||
| micro32r2.config | ||