Clément Léger 5ea6764d90 riscv: hwprobe: fix invalid sign extension for RISCV_HWPROBE_EXT_ZVFHMIN ... The current definition yields a negative 32bits signed value which result in a mask with is obviously incorrect. Replace it by using a 1ULL bit shift value to obtain a single set bit mask. Fixes: 5dadda5e6a ("riscv: hwprobe: export Zvfh[min] ISA extensions") Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20240409143839.558784-1-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2024-04-23 07:06:44 -07:00
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Kbuild	treewide: Add SPDX license identifier - Kbuild	2019-05-30 11:32:33 -07:00
auxvec.h	RISC-V: Update AT_VECTOR_SIZE_ARCH for new AT_MINSIGSTKSZ	2024-03-27 07:07:35 -07:00
bitsperlong.h	asm-generic: partially revert "Unify uapi bitsperlong.h for arm64, riscv and loongarch"	2023-08-17 14:51:20 +02:00
bpf_perf_event.h	riscv, bpf: Add missing uapi header for BPF_PROG_TYPE_PERF_EVENT programs	2019-12-19 16:03:31 +01:00
byteorder.h	treewide: add "WITH Linux-syscall-note" to SPDX tag of uapi headers	2019-07-25 11:05:10 +02:00
elf.h	riscv: Add remaining module relocations	2023-11-07 14:59:31 -08:00
hwcap.h	riscv: Extending cpufeature.c to detect V-extension	2023-06-08 07:16:35 -07:00
hwprobe.h	riscv: hwprobe: fix invalid sign extension for RISCV_HWPROBE_EXT_ZVFHMIN	2024-04-23 07:06:44 -07:00
kvm.h	KVM/riscv changes for 6.9	2024-03-11 10:10:48 -04:00
perf_regs.h	riscv: Add support for perf registers sampling	2019-09-05 00:48:58 -07:00
ptrace.h	Merge patch "RISC-V: Add ptrace support for vectors"	2023-09-08 11:24:38 -07:00
setup.h	riscv: Bump COMMAND_LINE_SIZE value to 1024	2023-03-01 18:35:43 -08:00
sigcontext.h	riscv: sigcontext: Correct the comment of sigreturn	2023-07-11 13:05:19 -07:00
ucontext.h	riscv: fix styling in ucontext header	2022-10-28 14:46:16 -07:00
unistd.h	RISC-V: Add a syscall for HW probing	2023-04-18 15:48:14 -07:00