152 lines
4.1 KiB
YAML
152 lines
4.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm's SPMI PMIC ADC5 Gen3
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maintainers:
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- Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
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description: |
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SPMI PMIC5 Gen3 voltage ADC (ADC) provides interface to clients to read
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voltage. It is a 16-bit sigma-delta ADC. It also performs the same thermal
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monitoring function as the existing ADC_TM devices.
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The interface is implemented on SDAM (Shared Direct Access Memory) peripherals
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on the master PMIC rather than a dedicated ADC peripheral. The number of PMIC
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SDAM peripherals allocated for ADC is not correlated with the PMIC used, it is
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programmed in FW (PBS) and is fixed per SOC, based on the SOC requirements.
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All boards using a particular (SOC + master PMIC) combination will have the
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same number of ADC SDAMs supported on that PMIC.
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properties:
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compatible:
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const: qcom,spmi-adc5-gen3
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reg:
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items:
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- description: SDAM0 base address in the SPMI PMIC register map
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- description: SDAM1 base address
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minItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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"#io-channel-cells":
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const: 1
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"#thermal-sensor-cells":
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const: 1
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interrupts:
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items:
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- description: SDAM0 end of conversion (EOC) interrupt
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- description: SDAM1 EOC interrupt
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minItems: 1
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patternProperties:
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"^channel@[0-9a-f]+$":
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type: object
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unevaluatedProperties: false
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$ref: /schemas/iio/adc/qcom,spmi-vadc-common.yaml
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description:
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Represents the external channels which are connected to the ADC.
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properties:
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qcom,decimation:
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enum: [ 85, 340, 1360 ]
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default: 1360
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qcom,hw-settle-time:
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enum: [ 15, 100, 200, 300, 400, 500, 600, 700,
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1000, 2000, 4000, 8000, 16000, 32000, 64000, 128000 ]
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default: 15
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qcom,avg-samples:
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enum: [ 1, 2, 4, 8, 16 ]
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default: 1
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qcom,adc-tm:
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description:
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ADC_TM is a threshold monitoring feature in HW which can be enabled
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on any ADC channel, to trigger an IRQ for threshold violation. In
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earlier ADC generations, it was implemented in a separate device
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(documented in Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml.)
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In Gen3, this feature can be enabled in the same ADC device for any
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channel and threshold monitoring and IRQ triggering are handled in FW
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(PBS) instead of another dedicated HW block.
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This property indicates ADC_TM monitoring is done on this channel.
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type: boolean
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- "#io-channel-cells"
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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pmic {
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#address-cells = <1>;
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#size-cells = <0>;
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adc@9000 {
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compatible = "qcom,spmi-adc5-gen3";
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reg = <0x9000>, <0x9100>;
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interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>,
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<0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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#io-channel-cells = <1>;
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#thermal-sensor-cells = <1>;
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/* PMK8550 Channel nodes */
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channel@3 {
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reg = <0x3>;
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label = "pmk8550_die_temp";
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qcom,pre-scaling = <1 1>;
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};
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channel@44 {
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reg = <0x44>;
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label = "pmk8550_xo_therm";
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qcom,pre-scaling = <1 1>;
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qcom,ratiometric;
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qcom,hw-settle-time = <200>;
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qcom,adc-tm;
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};
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/* PM8550 Channel nodes */
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channel@103 {
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reg = <0x103>;
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label = "pm8550_die_temp";
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qcom,pre-scaling = <1 1>;
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};
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/* PM8550B Channel nodes */
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channel@78f {
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reg = <0x78f>;
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label = "pm8550b_vbat_sns_qbg";
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qcom,pre-scaling = <1 3>;
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};
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/* PM8550VS_C Channel nodes */
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channel@203 {
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reg = <0x203>;
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label = "pm8550vs_c_die_temp";
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qcom,pre-scaling = <1 1>;
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};
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};
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};
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