Nick Desaulniers e8a170ff9a drm/amdgpu: enable -msse2 for GCC 7.1+ users ... A final attempt at enabling sse2 for GCC users. Orininally attempted in: commit 1011745073 ("drm/amd/display: add -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines") Reverted due to "reported instability" in: commit 193392ed9f ("Revert "drm/amd/display: add -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines"") Re-added just for Clang in: commit 0f0727d971 ("drm/amd/display: readd -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines") The original report didn't have enough information to know if the GPF was due to misalignment, but I suspect that it was. (The missing information was the disassembly of the function at the bottom of the trace, to see if the instruction pointer pointed to an instruction with 16B alignment memory operand requirements. The stack trace does show the stack was only 8B but not 16B aligned though, which makes this a strong possibility). Now that the stack misalignment issue has been fixed for users of GCC 7.1+, reattempt adding -msse2. This matches Clang. It will likely never be safe to enable this for pre-GCC 7.1 AND use a 16B aligned stack in these translation units. This is only a functional change for GCC 7.1+ users, and should be boot tested. Link: https://bugs.freedesktop.org/show_bug.cgi?id=109487 Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-10-30 11:56:20 -04:00
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Makefile	drm/amdgpu: enable -msse2 for GCC 7.1+ users	2019-10-30 11:56:20 -04:00
dc_dsc.c	drm/amd/display: Change DSC policy from slices per column to minimum slice height	2019-08-15 10:54:46 -05:00
dscc_types.h	…
qp_tables.h	…
rc_calc.c	…
rc_calc.h	…
rc_calc_dpi.c	…