d91680efca
Enable FEC in crtc_state, as soon as it's known it will be needed by DSC. This fixes the calculation of BW allocation overhead, in case DSC is enabled by falling back to it during the encoder compute config phase (vs. enabling FEC due to DSC being enabled on other streams). v2: - Enable FEC only in intel_dp_mst_find_vcpi_slots_for_bpp(), since only by that will crtc_state->port_clock be set, which in turn is needed by intel_dp_is_uhbr(). Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1) Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231030155843.2251023-11-imre.deak@intel.com |
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| drm | ||
| host1x | ||
| ipu-v3 | ||
| trace | ||
| vga | ||
| Makefile | ||