49 lines
2.1 KiB
JSON
49 lines
2.1 KiB
JSON
[
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{
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"ArchStdEvent": "BUS_ACCESS",
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"PublicDescription": "This event counts the number of data-beat accesses between the CPU and the external bus. This count includes accesses due to read, write, and snoop. Each beat of data is counted individually."
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},
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{
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"ArchStdEvent": "BUS_CYCLES",
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"PublicDescription": "This event counts bus cycles in the CPU. Bus cycles represent a clock cycle in which a transaction could be sent or received on the interface from the CPU to the external bus. Since that interface is driven at the same clock speed as the CPU, this event increments at the rate of CPU clock. Regardless of the WFE/WFI state of the PE, this event increments on each processor clock."
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},
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{
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"ArchStdEvent": "BUS_ACCESS_RD",
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"PublicDescription": "This event counts memory Read transactions seen on the external bus. Each beat of data is counted individually."
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},
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{
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"ArchStdEvent": "BUS_ACCESS_WR",
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"PublicDescription": "This event counts memory Write transactions seen on the external bus. Each beat of data is counted individually."
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},
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{
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"EventCode": "0x0154",
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"EventName": "BUS_REQUEST_REQ",
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"PublicDescription": "Bus request, request."
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},
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{
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"EventCode": "0x0155",
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"EventName": "BUS_REQUEST_RETRY",
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"PublicDescription": "Bus request, retry."
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},
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{
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"EventCode": "0x0198",
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"EventName": "L2_CHI_CBUSY0",
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"PublicDescription": "Number of RXDAT or RXRSP response received width CBusy of 0."
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},
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{
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"EventCode": "0x0199",
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"EventName": "L2_CHI_CBUSY1",
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"PublicDescription": "Number of RXDAT or RXRSP response received width CBusy of 1."
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},
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{
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"EventCode": "0x019a",
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"EventName": "L2_CHI_CBUSY2",
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"PublicDescription": "Number of RXDAT or RXRSP response received width CBusy of 2."
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},
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{
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"EventCode": "0x019b",
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"EventName": "L2_CHI_CBUSY3",
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"PublicDescription": "Number of RXDAT or RXRSP response received width CBusy of 3."
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}
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]
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