b756079846
AMD MDB IP supports Linked List (LL) mode as well as non-LL mode. The current code does not have the mechanisms to enable the DMA transactions using the non-LL mode. The following two cases are added with this patch: - For the AMD (Xilinx) only, when a valid physical base address of the device side DDR is not configured, then the IP can still be used in non-LL mode. For all the channels DMA transactions will be using the non-LL mode only. This, the default non-LL mode, is not applicable for Synopsys IP with the current code addition. - If the default mode is LL-mode, for both AMD (Xilinx) and Synosys, and if user wants to use non-LL mode then user can do so via configuring the peripheral_config param of dma_slave_config. Signed-off-by: Devendra K Verma <devendra.verma@amd.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260318070403.1634706-3-devendra.verma@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org> |
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| .. | ||
| amd_xdma.h | ||
| dw.h | ||
| edma.h | ||
| hsu.h | ||
| idma64.h | ||
| imx-dma.h | ||
| k3-event-router.h | ||
| k3-psil.h | ||
| k3-udma-glue.h | ||
| mxs-dma.h | ||
| pxa-dma.h | ||
| qcom-gpi-dma.h | ||
| qcom_adm.h | ||
| qcom_bam_dma.h | ||
| sprd-dma.h | ||
| ti-cppi5.h | ||
| xilinx_dma.h | ||
| xilinx_dpdma.h | ||