mirror-linux/drivers/clk/rockchip
Heiko Stuebner cd8b536663 clk: rockchip: rk3588: make refclko25m_ethX critical
Ethernet phys normally need a 25MHz refclk input. On a lot of boards
this is done with a dedicated 25MHz crystal. But the rk3588 CRU also
provides a means for that via the refclko25m_ethX clock outputs that
can be used for that function.

The mdio bus normally probes devices on the bus at runtime, by reading
specific phy registers. This requires the phy to be running and thus
also being supplied by its reference clock.

While there exist the possibility and dt-binding to declare these
input clocks for each phy in the phy-dt-node, this is only relevant
_after_ the phy has been detected and during the drivers probe-run.

This results in a chicken-and-egg-problem. The refclks in the CRU are
running on boot of course, but phy-probing can very well happen after
clk_disable_unused has run.

In the past I tried to make clock-handling part of the mdio bus code [0]
but that wasn't very well received, due to it being specific to OF and
clocks with the consensus being that resources needed for detection
need to be enabled before.

So to make probing ethernet phys using the internal refclks possible,
make those 2 clocks critical.

[0] https://lore.kernel.org/netdev/13590315.F0gNSz5aLb@diego/T/

Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Link: https://lore.kernel.org/r/20241214224820.200665-1-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-01-09 16:23:32 +01:00
..
Kconfig clk: rockchip: Add clock controller for the RK3576 2024-08-29 11:13:33 +02:00
Makefile clk: rockchip: implement linked gate clock support 2025-01-09 16:19:21 +01:00
clk-cpu.c clk: rockchip: Switch to use kmemdup_array() 2024-06-23 22:10:48 +02:00
clk-ddr.c clk: rockchip: Export rockchip_clk_register_ddrclk() 2020-09-22 15:16:37 +02:00
clk-half-divider.c clk: rockchip: Demote non-conformant kernel-doc header in half-divider 2021-01-26 00:24:05 +01:00
clk-inverter.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 2019-05-30 11:26:37 -07:00
clk-mmc-phase.c clk: rockchip: Remove an unused field in struct rockchip_mmc_clock 2024-05-04 12:38:02 +02:00
clk-muxgrf.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 2019-06-05 17:36:37 +02:00
clk-pll.c clk: rockchip: Add new pll type pll_rk3588_ddr 2024-08-29 11:13:28 +02:00
clk-px30.c clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage 2024-08-28 21:25:49 +02:00
clk-rk3036.c clk: rockchip: rk3036: Drop CLK_NR_CLKS usage 2024-08-28 21:25:49 +02:00
clk-rk3128.c clk: rockchip: rk3128: Add HCLK_SFC 2024-06-23 22:10:43 +02:00
clk-rk3188.c clk: rockchip: rk3188: Drop CLK_NR_CLKS usage 2024-06-27 21:04:40 +02:00
clk-rk3228.c clk: rockchip: rk3228: Drop CLK_NR_CLKS usage 2024-08-28 21:25:49 +02:00
clk-rk3288.c clk: rockchip: rk3288: Drop CLK_NR_CLKS usage 2024-08-28 21:25:49 +02:00
clk-rk3308.c clk: rockchip: rk3308: Drop CLK_NR_CLKS usage 2024-08-28 21:25:50 +02:00
clk-rk3328.c clk: rockchip: rk3328: Drop CLK_NR_CLKS usage 2024-08-28 21:25:50 +02:00
clk-rk3368.c clk: rockchip: rk3368: Drop CLK_NR_CLKS usage 2024-08-28 21:25:50 +02:00
clk-rk3399.c clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage 2024-08-28 21:25:50 +02:00
clk-rk3568.c clk: rockchip: rk3568: Add PLL rate for 724 MHz 2024-05-04 12:38:13 +02:00
clk-rk3576.c clk: rockchip: remove unused mclk_pdm0_p/pdm0_p definitions 2024-09-09 14:10:32 -07:00
clk-rk3588.c clk: rockchip: rk3588: make refclko25m_ethX critical 2025-01-09 16:23:32 +01:00
clk-rv1108.c clk: rockchip: support more core div setting 2021-03-21 11:10:58 +01:00
clk-rv1126.c Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next 2023-08-30 14:38:19 -07:00
clk.c clk: rockchip: implement linked gate clock support 2025-01-09 16:19:21 +01:00
clk.h clk: rockchip: implement linked gate clock support 2025-01-09 16:19:21 +01:00
gate-link.c clk: rockchip: implement linked gate clock support 2025-01-09 16:19:21 +01:00
rst-rk3576.c clk: rockchip: Add clock controller for the RK3576 2024-08-29 11:13:33 +02:00
rst-rk3588.c clk: rockchip: rk3588: Add reset line for HDMI Receiver 2024-04-10 07:10:40 +02:00
softrst.c clk: rockchip: add lookup table support 2022-11-14 15:35:07 +01:00