f513991b69
This rate allows to provide a low-jitter 72,4 MHz pixelclock for a custom eDP panel from the VPLL. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Link: https://lore.kernel.org/r/20240503153329.3906030-1-l.stach@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| clk-cpu.c | ||
| clk-ddr.c | ||
| clk-half-divider.c | ||
| clk-inverter.c | ||
| clk-mmc-phase.c | ||
| clk-muxgrf.c | ||
| clk-pll.c | ||
| clk-px30.c | ||
| clk-rk3036.c | ||
| clk-rk3128.c | ||
| clk-rk3188.c | ||
| clk-rk3228.c | ||
| clk-rk3288.c | ||
| clk-rk3308.c | ||
| clk-rk3328.c | ||
| clk-rk3368.c | ||
| clk-rk3399.c | ||
| clk-rk3568.c | ||
| clk-rk3588.c | ||
| clk-rv1108.c | ||
| clk-rv1126.c | ||
| clk.c | ||
| clk.h | ||
| rst-rk3588.c | ||
| softrst.c | ||