af3826db74
Current driver uses software CQ head pointer to poll on CQE header in memory to determine if CQE is valid. Software needs to make sure, that the reads of the CQE do not get re-ordered so much that it ends up with an inconsistent view of the CQE. To ensure that DMB barrier after read to first CQE cacheline and before reading of the rest of the CQE is needed. But having barrier for every CQE read will impact the performance, instead use hardware CQ head and tail pointers to find the valid number of CQEs. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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| actions | ||
| amlogic | ||
| brcmstb | ||
| cirrus | ||
| dove | ||
| ixp4xx | ||
| marvell/octeontx2 | ||
| mediatek | ||
| mmp | ||
| nxp | ||
| qcom | ||
| renesas | ||
| samsung | ||
| sunxi | ||
| ti | ||