Stephen Boyd c30cc9ffc1 Merge branches 'clk-rockchip', 'clk-thead', 'clk-microchip', 'clk-imx' and 'clk-qcom' into clk-next ... * clk-rockchip: clk: rockchip: rk3568: Add PLL rate for 132MHz * clk-thead: clk: thead: th1520-ap: Describe mux clocks with clk_mux clk: thead: th1520-ap: Correctly refer the parent of osc_12m clk: thead: Mark essential bus clocks as CLK_IGNORE_UNUSED * clk-microchip: clk: at91: sam9x7: update pll clk ranges * clk-imx: MAINTAINERS: Update i.MX Clock Entry clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR clk: imx95-blk-ctl: Rename lvds and displaymix csr blk clk: imx95-blk-ctl: Fix synchronous abort dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data * clk-qcom: (65 commits) dt-bindings: clock: qcom,sm4450-dispcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom,sm4450-camcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom,mmcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom,sm8150-camcc: Reference qcom,gcc.yaml dt-bindings: clock: qcom: Remove double colon from description clk: qcom: Add Video Clock controller (VIDEOCC) driver for Milos dt-bindings: clock: qcom: document the Milos Video Clock Controller clk: qcom: Add Graphics Clock controller (GPUCC) driver for Milos dt-bindings: clock: qcom: document the Milos GPU Clock Controller clk: qcom: Add Display Clock controller (DISPCC) driver for Milos dt-bindings: clock: qcom: document the Milos Display Clock Controller clk: qcom: Add Camera Clock controller (CAMCC) driver for Milos dt-bindings: clock: qcom: document the Milos Camera Clock Controller clk: qcom: Add Global Clock controller (GCC) driver for Milos dt-bindings: clock: qcom: document the Milos Global Clock Controller clk: qcom: common: Add support to register rcg dfs in qcom_cc_really_probe clk: qcom: gcc-x1e80100: Add missing video resets dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets clk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100 clk: qcom: videocc-sm8550: Allow building without SM8550/SM8560 GCC ...		2025-07-29 15:19:17 -07:00
..
Kconfig	clk: rockchip: Add clock controller for the RK3562	2025-03-02 17:51:51 +01:00
Makefile	clk: rockchip: rename gate-grf clk file	2025-05-13 20:30:15 +02:00
clk-cpu.c	clk: Fix typos	2025-07-26 23:49:18 -07:00
clk-ddr.c	clk: rockchip: Export rockchip_clk_register_ddrclk()	2020-09-22 15:16:37 +02:00
clk-gate-grf.c	clk: rockchip: rename gate-grf clk file	2025-05-13 20:30:15 +02:00
clk-half-divider.c	clk: rockchip: Demote non-conformant kernel-doc header in half-divider	2021-01-26 00:24:05 +01:00
clk-inverter.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157	2019-05-30 11:26:37 -07:00
clk-mmc-phase.c	clk: Fix typos	2025-07-26 23:49:18 -07:00
clk-muxgrf.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282	2019-06-05 17:36:37 +02:00
clk-pll.c	clk: Fix typos	2025-07-26 23:49:18 -07:00
clk-px30.c	clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage	2024-08-28 21:25:49 +02:00
clk-rk3036.c	clk: rockchip: rk3036: mark ddrphy as critical	2025-05-08 20:29:02 +02:00
clk-rk3128.c	clk: rockchip: rk3128: Add HCLK_SFC	2024-06-23 22:10:43 +02:00
clk-rk3188.c	clk: rockchip: rk3188: use PCLK_CIF0/1 clock IDs on RK3066	2025-02-26 17:52:48 +01:00
clk-rk3228.c	clk: rockchip: rk3228: Drop CLK_NR_CLKS usage	2024-08-28 21:25:49 +02:00
clk-rk3288.c	clk: rockchip: introduce auxiliary GRFs	2025-05-05 22:39:24 +02:00
clk-rk3308.c	clk: rockchip: rk3308: Drop CLK_NR_CLKS usage	2024-08-28 21:25:50 +02:00
clk-rk3328.c	clk: rockchip: introduce auxiliary GRFs	2025-05-05 22:39:24 +02:00
clk-rk3368.c	clk: rockchip: rk3368: Drop CLK_NR_CLKS usage	2024-08-28 21:25:50 +02:00
clk-rk3399.c	clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage	2024-08-28 21:25:50 +02:00
clk-rk3528.c	clk: rockchip: rk3528: add slab.h header include	2025-05-15 14:49:05 +02:00
clk-rk3562.c	clk: rockchip: Add clock controller for the RK3562	2025-03-02 17:51:51 +01:00
clk-rk3568.c	clk: rockchip: rk3568: Add PLL rate for 132MHz	2025-07-10 13:47:36 +02:00
clk-rk3576.c	I've recently moved computers (among other things) so I'm sending this from a	2025-05-30 09:15:40 -07:00
clk-rk3588.c	clk: rockchip: rk3588: Add PLL rate for 1500 MHz	2025-04-10 14:28:14 +02:00
clk-rv1108.c	clk: rockchip: support more core div setting	2021-03-21 11:10:58 +01:00
clk-rv1126.c	clk: rockchip: introduce auxiliary GRFs	2025-05-05 22:39:24 +02:00
clk.c	clk: rockchip: rename branch_muxgrf to branch_grf_mux	2025-05-13 20:30:15 +02:00
clk.h	clk: Fix typos	2025-07-26 23:49:18 -07:00
gate-link.c	clk: rockchip: implement linked gate clock support	2025-01-09 16:19:21 +01:00
rst-rk3528.c	clk: rockchip: rk3528: Add reset lookup table	2025-02-27 20:08:25 +01:00
rst-rk3562.c	clk: rockchip: Add clock controller for the RK3562	2025-03-02 17:51:51 +01:00
rst-rk3576.c	clk: rockchip: Add clock controller for the RK3576	2024-08-29 11:13:33 +02:00
rst-rk3588.c	clk: rockchip: rk3588: Add reset line for HDMI Receiver	2024-04-10 07:10:40 +02:00
softrst.c	clk: rockchip: add lookup table support	2022-11-14 15:35:07 +01:00