67 lines
1.6 KiB
YAML
67 lines
1.6 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mmc/wm,wm8505-sdhc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: WonderMedia SoC SDHCI Controller
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maintainers:
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- Alexey Charkov <alchark@gmail.com>
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allOf:
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- $ref: mmc-controller.yaml#
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properties:
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compatible:
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oneOf:
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- const: wm,wm8505-sdhc
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- items:
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- const: wm,wm8650-sdhc
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- const: wm,wm8505-sdhc
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- items:
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- const: wm,wm8750-sdhc
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- const: wm,wm8505-sdhc
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- items:
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- const: wm,wm8850-sdhc
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- const: wm,wm8505-sdhc
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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interrupts:
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items:
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- description: SDMMC controller interrupt
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- description: SDMMC controller DMA interrupt
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sdon-inverted:
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type: boolean
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description: All chips before (not including) WM8505 rev. A2 treated their
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"clock stop" bit (register offset 0x08 a.k.a. SDMMC_BUSMODE, bit 0x10)
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as "set 1 to disable SD clock", while all the later versions treated it
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as "set 0 to disable SD clock". Set this property for later versions of
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wm,wm8505-sdhc. On wm,wm8650-sdhc and later this property is implied and
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does not need to be set explicitly
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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mmc@d800a000 {
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compatible = "wm,wm8505-sdhc";
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reg = <0xd800a000 0x1000>;
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interrupts = <20>, <21>;
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clocks = <&sdhc>;
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bus-width = <4>;
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sdon-inverted;
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};
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