Commit Graph

12 Commits (2c142b63c8ee982cdfdba49a616027c266294838)

Author SHA1 Message Date
Marek Vasut c5f21e57e7 ARM: dts: renesas: r7s72100: Add missing unit address to bus node
Add missing unit address to bus node to fix the following DTC W=1
warning:

    arch/arm/boot/dts/renesas/r7s72100.dtsi:40.11-46.4: Warning (unit_address_vs_reg): /bus: node has a reg or ranges property, but no unit name

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260327234244.91707-5-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-04-27 11:14:30 +02:00
Geert Uytterhoeven aaee68616c ARM: dts: renesas: r7s72100: Move interrupt-parent to root node
Move the "interrupt-parent = <&gic>" property from the soc node to the
root node, and simplify "interrupts-extended = <&gic ...>" to
"interrupts = <...>".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://patch.msgid.link/6aaabd73f6732f932b5708b1036a9c398c44cd19.1759414774.git.geert+renesas@glider.be
2025-10-28 09:23:45 +01:00
Marek Vasut 256feb5be4 ARM: dts: renesas: r7s72100: Add boot phase tags
bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to describe various node usage during
boot phases with DT.  Add bootph-all for all nodes that are used in the
bootloader on Renesas RZ/A1 SoCs.

All SoCs require BSC bus, PFC pin control, and OSTM0 timer access during
all stages of the boot process, those are marked using bootph-all
property, and so is the SoC bus node which contains the PFC and OSTM
IPs.

Each board console UART is also marked as bootph-all to make it
available in all stages of the boot process.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250806150448.9669-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-08-12 09:38:53 +02:00
Geert Uytterhoeven b47325cc1f ARM: dts: renesas: r7s72100: Add DMA support to RSPI
Add DMA properties to the device nodes for Renesas Serial Peripheral
Interfaces.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/dfafc16b840630f20e75292d419479294558e173.1732098491.git.geert+renesas@glider.be
2024-12-11 11:33:27 +01:00
Wolfram Sang 83eb988437 ARM: dts: renesas: r7s72100: Add DMA support to MMCIF
Add DMA properties to the device node for the MMC Host Interface.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241015224801.2535-6-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-11-03 12:27:45 +01:00
Wolfram Sang d823e397f3 ARM: dts: renesas: r7s72100: Add DMAC node
Add a device node for the Direct Memory Access Controller on the RZ/A1H
SoC.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241015224801.2535-5-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-11-03 12:27:45 +01:00
Wolfram Sang 43a576ac84 ARM: dts: renesas: r7s72100: 'bus-width' is a board property
Do not set 'bus-width' in the SoC-include DTSI. It must be set in the
board DTS file. No regressions because MMCIF was not enabled yet for
this SoC.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240928092953.2982-7-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-07 10:43:50 +02:00
Wolfram Sang 625d8daaba ARM: dts: renesas: Add proper node names to (L)BSC devices
(L)BSC must have a "bus" node name [1] and no unit-address because
there is no reg-property. Fix these entries.

[1] lbsc: $nodename:0: 'lbsc' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$'

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240926103340.16909-5-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-07 10:41:09 +02:00
Wolfram Sang b3daf6194e ARM: dts: renesas: Remove 'reg-io-width' properties from MMCIF nodes
The driver does not use this property and all upstream SoCs use the same
value anyhow. Remove it and get rid of a lot of dtbs_check warnings.
Tested with a Lager (R-Car H2) board and with the soon to be added
Genmai (RZA1) MMCIF support.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240925150904.3582-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-01 14:19:28 +02:00
Lad Prabhakar 7db74b65a9 ARM: dts: renesas: r7s72100: Add interrupt-names to SCIF nodes
Add "interrupt-names" properties to SCIF nodes for clarity.

This allows us to update the DT bindings to mark the "interrupt-names"
property required for all SoCs which have multiple interrupts, and to
validate the DTBs using dtbs_check.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240318174345.46824-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-03-26 09:22:41 +01:00
Geert Uytterhoeven 175f197116 ARM: dts: renesas: r7s72100: Add BSC node
Add a minimal device node for the Bus State Controller (BSC) on the
RZ/A1H SoC, to be extended by board DTS files for devices residing in
the BSC external address space.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ccab4fa198225edcd3750f62532a1ee3c6d2a109.1693481518.git.geert+renesas@glider.be
2023-09-25 09:19:20 +02:00
Rob Herring 724ba67515 ARM: dts: Move .dts files to vendor sub-directories
The arm dts directory has grown to 1559 boards which makes it a bit
unwieldy to maintain and use. Past attempts stalled out due to plans to
move .dts files out of the kernel tree. Doing that is no longer planned
(any time soon at least), so let's go ahead and group .dts files by
vendors. This move aligns arm with arm64 .dts file structure.

There's no change to dtbs_install as the flat structure is maintained on
install.

The naming of vendor directories is roughly in this order of preference:
- Matching original and current SoC vendor prefix/name (e.g. ti, qcom)
- Current vendor prefix/name if still actively sold (SoCs which have
  been aquired) (e.g. nxp/imx)
- Existing platform name for older platforms not sold/maintained by any
  company (e.g. gemini, nspire)

The whole move was scripted with the exception of MAINTAINERS and a few
makefile fixups.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Paul Barker <paul.barker@sancloud.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Nick Hawkins <nick.hawkins@hpe.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Peter Rosin <peda@axentia.se>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Romain Perier <romain.perier@gmail.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2023-06-21 11:39:50 -06:00