Make pins-are-numbered optional and deprecate it
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221129023401.278780-4-bero@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Remove the check for the unnecessary pins-are-numbered Devicetree property.
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20221129023401.278780-2-bero@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Enable PWM feature on Intel pin control IPs
The following is an automated git shortlog grouped by driver:
intel:
- Enumerate PWM device when community has a capability
pwm:
- lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe()
- lpss: Allow other drivers to enable PWM LPSS
- lpss: Include headers we are the direct user of
- lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS
- Add a stub for devm_pwmchip_add()
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Merge tag 'intel-pinctrl-v6.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v6.2-2
* Enable PWM feature on Intel pin control IPs
The following is an automated git shortlog grouped by driver:
intel:
- Enumerate PWM device when community has a capability
pwm:
- lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe()
- lpss: Allow other drivers to enable PWM LPSS
- lpss: Include headers we are the direct user of
- lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS
- Add a stub for devm_pwmchip_add()
The D1 pin controller contains muxes for two CAN buses. While the CAN
bus controllers are only documented for the T113 SoC, the pin controller
is the same across all SoC variants.
Signed-off-by: Fabien Poussin <fabien.poussin@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20221126191636.6673-1-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The kernel robot using sparse is complaining like this:
drivers/pinctrl/pinctrl-loongson2.c:212:21: sparse:
sparse: incorrect type in argument 1 (different address spaces) @@
expected void const volatile [noderef] __iomem *addr @@
got void *[noderef] __iomem reg @@
(...)
I think the problem is simply that the register base is defined
as void * __iomem instead of void __iomem * and this is because
of the way const correctness works with pointer infix order.
Fix it up. I think.
Reported-by: kernel test robot <lkp@intel.com>
Cc: zhanghongchen <zhanghongchen@loongson.cn>
Cc: Yinbo Zhu <zhuyinbo@loongson.cn>
Fixes: f73f88acbc ("pinctrl: pinctrl-loongson2: add pinctrl driver support")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
of_node_put() needs to be called when jumping out of the loop, since
for_each_available_child_of_node() will increase the refcount of node.
Fixes: c7289500e2 ("pinctrl: pinconf-generic: scan also referenced phandle node")
Signed-off-by: ZhangPeng <zhangpeng362@huawei.com>
Link: https://lore.kernel.org/r/20221125070156.3535855-1-zhangpeng362@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some of the Communities may have PWM capability. In such cases,
enumerate the PWM device via respective driver. A user is still
responsible for setting correct pin muxing for the line that
needs to output the signal.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
The pwm_lpss_probe() uses managed resources. Show this to
the users explicitly by adding devm prefix to its name.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
The PWM LPSS device can be embedded in another device.
In order to enable it, allow that drivers to probe
a corresponding device.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
For the sake of integrity, include headers we are the direct
user of.
Replace the inclusion of device.h by a forward declaration
of struct device plus a (cheaper) of types.h as device.h is
an expensive include (measured in compiler effort).
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
The MAX_PWMS definition is already being used by the PWM core.
Using the same name in the certain driver confuses people
and potentially can clash with it.
Hence, rename it by adding LPSS prefix.
Reported-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
The devm_pwmchip_add() can be called by a module that optionally
instantiates PWM chip. In the case of CONFIG_PWM=n, the compilation
can't be performed. Hence, add a necessary stub.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Since for_each_available_child_of_node() will increase the refcount of
node, we need to call of_node_put() manually when breaking out of the
iteration.
Fixes: d4c34d09ab ("pinctrl: Add RISC-V Canaan Kendryte K210 FPIOA driver")
Signed-off-by: ZhangPeng <zhangpeng362@huawei.com>
Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Link: https://lore.kernel.org/r/20221122075853.2496680-1-zhangpeng362@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The current pattern for SX1503 and SX1509Q with 16 GPIOs only matches
"gpio0", "gpio1", and "gpio5" instead of "gpio0" to "gpio15" included.
Fix these patterns to match the whole 16 GPIO line names.
Fixes: 29c10bcec5 ("dt-bindings: pinctrl: convert semtech,sx150xq bindings to dt-schema")
Reported-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20221121-sx150xq_bindings_fixup-v1-0-e754f183b611@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fixes following issues introduced in a previous commit
to clarify values for pin config pull up and down types.
- replace spaces with tabs to be consistent with rest of the doc
- use capitalization for unit (ohms -> Ohms)
Signed-off-by: Niyas Sait <niyas.sait@linaro.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20221117123542.1154252-1-niyas.sait@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If CONFIG_PINCTRL_LOONGSON2=y and CONFIG_OF is not set,
gcc complained about undefined reference:
drivers/pinctrl/pinctrl-loongson2.o: In function `pinconf_generic_dt_node_to_map_all':
pinctrl-loongson2.c:(.text+0x1c4): undefined reference to
`pinconf_generic_dt_node_to_map'
To fix this error, add depends on OF to
config PINCTRL_LOONGSON2.
Fixes: f73f88acbc ("pinctrl: pinctrl-loongson2: add pinctrl driver support")
Signed-off-by: Ren Zhijie <renzhijie2@huawei.com>
Link: https://lore.kernel.org/r/20221121132608.230645-1-renzhijie2@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Use dynamic GPIO base on combined pincctrl/gpio controllers on
SH/R-Mobile SoCs,
- Miscellaneous improvements.
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Merge tag 'renesas-pinctrl-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v6.2
- Use dynamic GPIO base on combined pincctrl/gpio controllers on
SH/R-Mobile SoCs,
- Miscellaneous improvements.
* Add Intel Moorefield pin control driver
* Deduplicate COMMUNITY() macro in the Intel pin control drivers
* Switch Freescale GPIO driver to use fwnode instead of of_node
* Miscellaneous clenups here and there
The following is an automated git shortlog grouped by driver:
alderlake:
- Deduplicate COMMUNITY macro code
cannonlake:
- Deduplicate COMMUNITY macro code
device property:
- Introduce fwnode_device_is_compatible() helper
icelake:
- Deduplicate COMMUNITY macro code
intel:
- Add Intel Moorefield pin controller support
- Use temporary variable for struct device
- Use str_enable_disable() helper
merrifield:
- Use temporary variable for struct device
qcom:
- lpass-lpi: Add missed bitfield.h
soc:
- fsl: qe: Switch to use fwnode instead of of_node
sunrisepoint:
- Deduplicate COMMUNITY macro code
tigerlake:
- Deduplicate COMMUNITY macro code
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Merge tag 'intel-pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v6.2-1
* Add Intel Moorefield pin control driver
* Deduplicate COMMUNITY() macro in the Intel pin control drivers
* Switch Freescale GPIO driver to use fwnode instead of of_node
* Miscellaneous clenups here and there
The following is an automated git shortlog grouped by driver:
alderlake:
- Deduplicate COMMUNITY macro code
cannonlake:
- Deduplicate COMMUNITY macro code
device property:
- Introduce fwnode_device_is_compatible() helper
icelake:
- Deduplicate COMMUNITY macro code
intel:
- Add Intel Moorefield pin controller support
- Use temporary variable for struct device
- Use str_enable_disable() helper
merrifield:
- Use temporary variable for struct device
qcom:
- lpass-lpi: Add missed bitfield.h
soc:
- fsl: qe: Switch to use fwnode instead of of_node
sunrisepoint:
- Deduplicate COMMUNITY macro code
tigerlake:
- Deduplicate COMMUNITY macro code
Since commit 502df79b86 ("gpiolib: Warn on drivers still using
static gpiobase allocation") in gpio/for-next, one or more warnings are
printed during boot on systems where the pin controller also provides
GPIO functionality:
gpio gpiochip0: Static allocation of GPIO base is deprecated, use dynamic allocation.
Fix this for ARM-based SH/R-Mobile SoCs by:
1. Taking into account a non-zero GPIO base in the various GPIO chip
callbacks,
2. Switching to dynamic allocation of the GPIO base when support for
legacy function GPIOs is not enabled.
On SuperH SoCs using legacy function GPIOs, the GPIO bases of the GPIO
controller and the GPIO function controller must not be changed, as all
board files rely on the fixed GPIO_* and GPIO_FN_* definitions provided
by the various <cpu/sh*.h> header files.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/df2cf30ac4c3cbee726799f32b727c1ebe62819c.1668000684.git.geert+renesas@glider.be
PIN_CONFIG_BIAS_PULL_DOWN and PIN_CONFIG_BIAS_PULL_UP values can
be custom or an SI unit such as ohms
Signed-off-by: Niyas Sait <niyas.sait@linaro.org>
Link: https://lore.kernel.org/r/20221115175415.650690-3-niyas.sait@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the Loongson-2 pinctrl binding with DT schema format using
json-schema.
Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn>
Link: https://lore.kernel.org/r/20221114024942.8111-2-zhuyinbo@loongson.cn
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Loongson-2 SoC has a few pins that can be used as GPIOs or take
multiple other functions. Add a driver for the pinmuxing.
There is currently no support for GPIO pin pull-up and pull-down.
Signed-off-by: zhanghongchen <zhanghongchen@loongson.cn>
Co-developed-by: Yinbo Zhu <zhuyinbo@loongson.cn>
Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn>
Link: https://lore.kernel.org/r/20221114024942.8111-1-zhuyinbo@loongson.cn
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Apparently RK3588 pinctrl has 13 different device functions, but dt-validate
only checks for pin configuration being referenced so I did not notice.
Fixes: ed1f77b783 ("dt-bindings: pinctrl: rockchip: increase max amount of device functions")
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20221021172012.87954-1-sebastian.reichel@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This converts the Semtech SX150Xq bindings to dt-schemas, add necessary
bindings documentation to cover all differences between HW variants
and current bindings usage.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221005-mdm9615-sx1509q-yaml-v3-0-e8b349eb1900@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Convert Qualcomm MSM8976 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Changes during conversion: update the list of non-mux pins (like sdc1)
to match Linux driver.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20221110085230.15108-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
First of all, while for_each_maps() is private to pin control subsystem
it's still better to have it put into a namespace.
Besides that, users are not relying on iterator variable, so hide it
inside for-loop.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20221111120048.42968-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tegra194 has two separate instances of the pin controller, one called
AON (in the always-on domain) and another called "main". Instead of
treating them as a single pin controller, split them up into two
separate controllers. Doing so allows the mapping between the pinmux
and GPIO controllers to be trivial identity mappings and more cleanly
separates the AON from the main IP blocks.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20221104142345.1562750-4-thierry.reding@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Convert Qualcomm MSM8960 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221109105140.48196-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Convert Qualcomm IPQ8074 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221108142357.67202-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Convert Qualcomm MSM8660 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107185931.22075-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
It's slightly better to read when compound literal data and type
are separated by a space.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Link: https://lore.kernel.org/r/20221109152356.39868-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Rename the header guard of mt6795-pinfunc.h from __DTS_MT8173_PINFUNC_H to
__DTS_MT6795_PINFUNC_H what corresponding with the file name.
Fixes: 81557a7156 ("dt-bindings: pinctrl: Add MediaTek MT6795 pinctrl bindings")
Signed-off-by: Wei Li <liwei391@huawei.com>
Link: https://lore.kernel.org/r/20221108094529.3597920-1-liwei391@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pad names for the i.MXRT1050 were incorrect. Fix them.
Cc: Giulio Benetti <giulio.benetti@benettiengineering.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Link: https://lore.kernel.org/r/20221107071511.2764628-7-Mr.Bossman075@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Both the i.MXRT1170 and 1050 have the same GPT timer as "fsl,imx6dl-gpt"
Add i.MXRT to the compatible list.
Cc: Giulio Benetti <giulio.benetti@benettiengineering.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20221107071511.2764628-4-Mr.Bossman075@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Recently the imxrt1050 was added but the cpu compatible node wasn't
added. Add both i.MXRT1170 and 1050 compatibles to fsl.yaml.
Cc: Giulio Benetti <giulio.benetti@benettiengineering.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221107071511.2764628-2-Mr.Bossman075@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Commit fb34a9ae38 ("pinctrl: mediatek: support rsel feature")
add SoC specify 'pull_type' attribute for bias configuration.
This patch add pull_type attribute to pinctrl-mt7986.c, and make
bias_set_combo and bias_get_combo available to mediatek MT7986 SoC.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221106080114.7426-7-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Commit fb34a9ae38 ("pinctrl: mediatek: support rsel feature")
introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo
and mtk_pinconf_bias_get_combo, and make the functions able to support
almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c.
This patch enables pinctrl_moore to support these functions.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221106080114.7426-6-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Correct the bias-pull-up, bias-pull-down and bias-disable register
offset of mt7986 pin-42 to pin-49, in the original driver, the
relative offset value was erroneously decremented by 1.
Fixes: 360de67280 ("pinctrl: mediatek: add support for MT7986 SoC")
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221106080114.7426-5-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since the bias-pull-{up,down} attribute already defines in pinctrl driver
of mediatek MT7986 SoC, this patch updates bindings to support mediatek
common bias-pull* function.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221106080114.7426-4-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix mmc and uart pins after uart splitting.
Some pinmux pins of the mt7986 pinctrl driver is composed of multiple
pinctrl groups, the original binding only allows one pinctrl group
per dts node, this patch sets "maxItems" for these groups and add new
examples to the binding documentation.
Fixes: 65916a1ca9 ("dt-bindings: pinctrl: update bindings for MT7986 SoC")
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221106080114.7426-3-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Bernhard Rosenkränzer